參數(shù)資料
型號: SE97BTP,547
廠商: NXP Semiconductors
文件頁數(shù): 34/53頁
文件大小: 386K
描述: IC TEMP SENSOR DIMM 8HWSON
產(chǎn)品培訓(xùn)模塊: I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標(biāo)準(zhǔn)包裝: 1
功能: 溫度監(jiān)控系統(tǒng)(傳感器),DIMM DDR 內(nèi)存
傳感器類型: 內(nèi)部
感應(yīng)溫度: -40°C ~ 125°C
精確度: ±3°C(最小值)
拓?fù)洌?/td> ADC(三角積分型),比較器,寄存器庫
輸出類型: I²C?/SMBus?
輸出警報(bào):
輸出風(fēng)扇:
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 8-WSON
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 847 (CN2011-ZH PDF)
其它名稱: 568-5055-6
SE97B_1
?NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01  27 January 2010
34 of 53
NXP Semiconductors
SE97B
DDR memory module temp sensor with integrated SPD
[1]   When the part comes out of shutdown, the state of the EVENT
 pin will not change until after the first
temperature conversion. When the part enters shutdown, the ACT (TEMP[15]), AAW (TEMP[14]) and BAW
(TEMP[13]) bits (flip-flops) will be cleared.
[2]   The STTS424E02 allows clearing the interrupt when in comparator mode, but the other competitors do not.
 
[1]   SMBus Time-out.
0  enabled (default)
1  disabled
[2]   Shutdown time-out.
0  SMBus Time-out disabled when SHMD = 1
1  SMBus Time-out enabled when SHMD = 1 (default)
[3]   Thermal Sensor Shutdown mode.
0  active (default)
1  shutdown
1
RFU
reserved; always 0
0
DisableARA
Disable SMBus Alert Response Address (ARA).
0  SMBus ARA is enabled
1  disable SMBus ARA (default)
When either of the Critical Trip or Alarm Window lock bits is set, this bit
cannot be altered until unlocked.
Table 27.   SMBus Time-out register bit description &continued
Bit
Symbol
Description
Table 28.   SMBus register setting guide
Disable
Timeout
[1]
Enable
SDTO
[2]
SHMD
[3]
Thermal sensor
behavior
SPD behavior
Power mode
Use
0
X
0
TS is active and
SMBus TO is on
SPD read/write and
SMBus TO is on
Full power,
oscillator is running
JEDEC - SMBus for
TS and SPD
(like SE97 if TS is on)
1
X
0
TS is active and
SMBus TO is off
SPD read/write and
SMBus TO is off
Full power,
oscillator is running
I
2
C-bus - no SMBus
TO
0
1
1
TS is disabled and
SMBus TO is on
SPD read/write and
SMBus TO is on
Lower power,
oscillator is off unless
bus active or write to
SPD
JEDEC - SMBus for
TS and SPD
1
1
1
TS is disabled and
SMBus TO is off
SPD low power
read/write and
SMBus TO is off
Lower power,
oscillator is off unless
write to the SPD
I
2
C-bus - no SMBus
TO
X
0
1
TS is disabled and
SMBus TO is off
SPD low power
read-only and
SMBus TO is off
Lowest power,
oscillator is off all
the time
I
2
C-bus - no SMBus
TO (like SE97 if TS is
off)
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