參數(shù)資料
型號(hào): SE97BTP,547
廠商: NXP Semiconductors
文件頁(yè)數(shù): 33/53頁(yè)
文件大小: 386K
描述: IC TEMP SENSOR DIMM 8HWSON
產(chǎn)品培訓(xùn)模塊: I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標(biāo)準(zhǔn)包裝: 1
功能: 溫度監(jiān)控系統(tǒng)(傳感器),DIMM DDR 內(nèi)存
傳感器類(lèi)型: 內(nèi)部
感應(yīng)溫度: -40°C ~ 125°C
精確度: ±3°C(最小值)
拓?fù)洌?/td> ADC(三角積分型),比較器,寄存器庫(kù)
輸出類(lèi)型: I²C?/SMBus?
輸出警報(bào):
輸出風(fēng)扇:
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 8-WFDFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 8-WSON
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 847 (CN2011-ZH PDF)
其它名稱(chēng): 568-5055-6
SE97B_1
?NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01  27 January 2010
33 of 53
NXP Semiconductors
SE97B
DDR memory module temp sensor with integrated SPD
8.9   SMBUS  SMBus register (22h, 8-bit read/write)
 
 
Table 26.   SMBUS - SMBus Time-out register bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
RFU
Default
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit
7
6
5
4
3
2
1
0
Symbol
Disable
Timeout
RFU
Enable
SDTO
Event
Sleep
State
IntrClear
Mode
Flag
Update
Mode
RFU
Disable
ARA
Default
0
0
1
1
0
0
0
1
Access
R/W
R
R/W
R/W
R/W
R/W
R
R/W
Table 27.   SMBus Time-out register bit description
Bit
Symbol
Description
15:8
RFU
reserved; always 0
7
DisableTimeout   Disable SMBus time-out.
0  SMBus time-out is enabled (default)
1  SMBus time-out is disabled
When either of the Critical Trip or Alarm Window lock bits is set, this bit
cannot be altered until unlocked.
6
RFU
reserved; always 0
5
EnableSDTO
SMBus time-out during Shutdown (CONFIG[8]).
0  disable SMBus time-out
1  enable SMBus time-out (default)
Remark: DisableTimeout bit must be a logic 0 to enable this feature.
When either Critical Trip or Alarm Window lock bits are set, this bit
cannot be altered until unlocked.
4
EventSleep
State
[1]
State of EVENT
 output when SHMD bit is set.
0  EVENT
 pin state is frozen
1  EVENT
 pin is de-asserted, state based on Polarity bit (default)
When either Critical Trip or Alarm Window lock bits are set, this bit
cannot be altered until unlocked.
3
IntrClear
Mode
[2]
Interrupt Flop Clearing Mode.
0  allow clearing interrupt flop while in comparator mode (default)
1  disable clearing interrupt flow while in comparator mode
When either Critical Trip or Alarm Window lock bits are set, this bit
cannot be altered until unlocked.
2
FlagUpdate
Mode
Update AAW, BAW and ACT flags after each new temperature
conversion.
0  update AAW, BAW and ACT flags continuously (default)
1  update flags with new temperature conversion
When either Critical Trip or Alarm Window lock bits are set, this bit
cannot be altered until unlocked.
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