參數資料
型號: SE97BTP,547
廠商: NXP Semiconductors
文件頁數: 25/53頁
文件大?。?/td> 386K
描述: IC TEMP SENSOR DIMM 8HWSON
產品培訓模塊: I²C Bus Fundamentals
特色產品: NXP - I2C Interface
標準包裝: 1
功能: 溫度監(jiān)控系統(傳感器),DIMM DDR 內存
傳感器類型: 內部
感應溫度: -40°C ~ 125°C
精確度: ±3°C(最小值)
拓撲: ADC(三角積分型),比較器,寄存器庫
輸出類型: I²C?/SMBus?
輸出警報:
輸出風扇:
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-WFDFN 裸露焊盤
供應商設備封裝: 8-WSON
包裝: 標準包裝
產品目錄頁面: 847 (CN2011-ZH PDF)
其它名稱: 568-5055-6
SE97B_1
?NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01  27 January 2010
25 of 53
NXP Semiconductors
SE97B
DDR memory module temp sensor with integrated SPD
8
SHMD
Shutdown Mode.
0  Temperature Sensor is active and converting (default).
1  disabled Temperature Sensor will not generate interrupts or update
the temperature data.
When shut down, the thermal sensor diode and ADC are disabled to save
power, no events will be generated. When either of the Critical Trip or Alarm
Window lock bits is set, this bit cannot be set until unlocked. However, it can
be cleared at any time. When in shutdown mode, the SE97B will still respond
to commands normally.
When coming out of shutdown, the EVENT
 output remains de-asserted as a
new temperature conversion is done. Hysteresis is subtracted from the alarm
thresholds if the temperature is falling but not used if the temperature is
rising. The temperature trend will not be determined until at least two
temperature conversions are done. Since all the alarm threshold flags
(TEMP bits 13, 14, 15) are cleared with coming out of shutdown, it was
decided to only apply hysteresis to the lower alarm threshold calculations
when determining after the initial temperature conversion if the EVENT
should assert. After the second temperature conversion the direction of
temperature is known and TEMP bits 13, 14 or 15 are changed as required
and the EVENT
 is asserted as required.
7
CTLB
Critical Trip Lock bit.
0  Critical Alarm Trip register is not locked and can be altered (default)
1  Critical Alarm Trip register settings cannot be altered
This bit is initially cleared. When set, this bit will return a 1, and remains
locked until cleared by internal Power-on reset. This bit can be written with a
single write and does not require double writes.
6
AWLB
Alarm Window Lock bit.
0  Upper and Lower Alarm Trip registers are not locked and can be
altered (default)
1  Upper and Lower Alarm Trip registers setting cannot be altered
This bit is initially cleared. When set, this bit will return a 1 and remains
locked until cleared by internal power-on reset. This bit can be written with a
single write and does not require double writes.
5
CEVNT
Clear EVENT
 (write only).
0  no effect (default)
1  clears active EVENT
 in Interrupt mode. Writing to this register has no
effect in Comparator mode.
If SMBUS[0] is a logic 0, the SMBus Alert Response Address (ARA)
command can be sent to also clear the EVENT
 output. When read, this
register always returns zero.
4
ESTAT
EVENT
 Status (read only).
0  EVENT
 output condition is not being asserted by this device (default)
1  EVENT
 output pin is being asserted by this device due to Alarm
Window or Critical Trip condition
The actual event causing the event can be determined from the Read
Temperature register. Interrupt Events can be cleared by writing to the Clear
EVENT
 bit (CEVNT) or SMBus Alert Response. Writing to this bit will have
no effect.
Table 13.   Configuration register (address 01h) bit description &continued
Bit
Symbol
Description
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