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參數(shù)資料
| 型號(hào)： | SDA9400 |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Scan Rate Converter using Embedded DRAM Technology Units |
| 中文描述： | 掃描頻率轉(zhuǎn)換器采用嵌入式DRAM技術(shù)股 |
| 文件頁(yè)數(shù)： | 9/94頁(yè) |
| 文件大小： | 1180K |
| 代理商： | SDA9400 |
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SDA 9400
Micronas
9
Preliminary Data Sheet
5
Pin description
Pin No.
2,8,24,42,55
9,25,41,56
36,52,58
35,51,53,57,
59
43,..,50
31,..,34;37,...,
40
Name
VSS1
VDD1
VSS2
VDD2
Type
S
S
S
S
Description
Supply voltage (
V
SS
= 0 V )
Supply voltage (
V
DD
= 3.3 V )
Supply voltage (
V
SS
= 0 V )
Supply voltage (
V
DD
= 3.3 V )
YIN0...7
UVIN0...7
I/TTL
I/TTL
Data input Y (see input data format)
Data input UV (for 4:2:2 parallel, see input data format)
PD
I/TTL
(for CCIR 656, see input data format)
System reset. The RESET input is low active. In order to
ensure correct operation a
"
Power On Reset
"
must be
performed. The RESET pulse must have a minimum
duration of two clock periods of the system clock CLK1.
H-Sync input
30
RESET
23
HIN
I/TTL
PD
I/TTL
(only for full CCIR 656)
V-Sync input
22
VIN
PD
I/TTL
I/O
I
I/TTL
O/TTL
O/TTL
O/TTL
I/O/
TTL
(only for full CCIR 656)
Synchronization enable input
I
2
C-Bus data line (5V ability)
I
2
C-Bus clock line (5V ability)
System clock 1
Data output UV (see output data format)
Data output Y (see output data format)
Horizontal active video output
EXSYN=0 (I2C-bus parameter): V-Sync output
29
21
20
54
17,..,10
7,..,3;1;64;63
62
61
SYNCEN
SDA
SCL
CLK1
UVOUT0...7
YOUT0...7
HREF
VOUT/
VEXT
HOUT/
EXSYN=1: External V-Sync input for output part
EXSYN=0 (I2C-bus parameter): H-Sync output
60
HEXT
INTERLACED
X1 / CLK2
X2
CLKOUT
I/O/
TTL
EXSYN=1: External H-Sync input for output part
Interlace signal for AC coupled vertical deflection
Crystal connection / System clock 2
O/ANA Crystal connection
O/TTL
Clock output (depends on I2C parameters CLK11EN,
CLK21EN, FREQR, see also
Clock concept
on Page 37)
I/TTL
Test input, connect to
V
SS
for normal operation
18
28
27
26
O/TTL
I/TTL
19
TEST
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