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參數(shù)資料
| 型號： | SDA9400 |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Scan Rate Converter using Embedded DRAM Technology Units |
| 中文描述： | 掃描頻率轉(zhuǎn)換器采用嵌入式DRAM技術(shù)股 |
| 文件頁數(shù)： | 5/94頁 |
| 文件大小： | 1180K |
| 代理商： | SDA9400 |
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SDA 9400
Micronas
5
Preliminary Data Sheet
1
General description
The SDA 9400 is a new component of the Micronas MEGAVISION
IC set in a 0.35 μm embedded
DRAM technology (frame memory embedded). The SDA 9400 is pin compatible to the SDA 9401
(field memory embedded). The SDA 9400 comprises all main functionalities of a digital featurebox
in one monolithic IC.
The scan rate conversion to 100/120 Hz interlaced (50/60 Hz progressive) is based on a motion
adaptive algorithm. The scan rate converted picture can be vertically expanded. The SDA 9400 has
a freerunning mode, therefore features like scan rate conversion to e.g. 70, 75 Hz with joint lines or
multiple picture display (e.g. tuner scan) are possible.
Due to the frame based signal processing, the noise reduction has been greatly improved.
Furthermore separate motion detectors for luminance and chrominance have been implemented.
For automatic controlling of the noise reduction parameters a noise measurement algorithm is
included, which measures the noise level in the picture or in the blanking period. In addition a spatial
noise reduction is implemented, which reduces the noise even in the case of motion. The input
signal can be compressed horizontally and vertically with a certain number of factors. Therefore split
screen is supported.
Beside these additional functions like coloured background, windowing and flashing are
implemented.
2
Features
Two input data formats
- 4:2:2 luminance and chrominance parallel (2 x 8 wires)
- ITU-R 656 data format (8 wires)
Two different representations of input chrominance data
- 2‘s complement code
- Positive dual code
Flexible input sync controller
Flexible compression of the input signal
- Digital vertical compression of the input signal (1.0, 1.25, 1.5, 1.75, 2.0, 3.0, 4.0)
- Digital horizontal compression of the input signal (1.0, 2.0, 4.0)
Noise reduction
- Motion adaptive spatial and temporal noise reduction (3D-NR)
- Temporal noise reduction for luminance frame based or field based
- Temporal noise reduction for chrominance field based
- Separate motion detectors for luminance and chrominance
- Flexible programming of the temporal noise reduction parameters
- Automatic measurement of the noise level (5 bit value, readable by I2C bus)
3-D motion detection
- High performance motion detector for scan rate conversion
- Global motion detection flag (readable by I2C bus)
- Movie mode and phase detector (readable by I2C bus)
相關(guān)PDF資料 |
PDF描述 |
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| SDA9410-B13 | Display Processor and Scan Rate Converter using Embedded DRAM Technology Units |
| SDA9415-B13 | Display Processor and Scan Rate Converter |
| SDA9488X | Cost-effective Picture-In-Picture ICs |
| SDA9588X | Cost-effective Picture-In-Picture ICs |
| SDA9489X | PIP IV Advanced SOPHISTICUS High-End Picture-In-Picture ICs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SDA9401 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Scan Rate Converter using Embedded DRAM Technology Units |
| SDA9410-B13 | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Display Processor and Scan Rate Converter using Embedded DRAM Technology Units |
| SDA9415-B13 | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Display Processor and Scan Rate Converter |
| SDA9488X | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Cost-effective Picture-In-Picture ICs |
| SDA9489X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PIP IV Advanced SOPHISTICUS High-End Picture-In-Picture ICs |
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