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參數(shù)資料
| 型號(hào)： | SDA9400 |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Scan Rate Converter using Embedded DRAM Technology Units |
| 中文描述： | 掃描頻率轉(zhuǎn)換器采用嵌入式DRAM技術(shù)股 |
| 文件頁(yè)數(shù)： | 16/94頁(yè) |
| 文件大小： | 1180K |
| 代理商： | SDA9400 |
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SDA 9400
Micronas
16
Preliminary Data Sheet
Input sync formats
The amplitude resolution for each input signal component is 8 bit, the maximum clock frequency is
27 MHz. Consequently the SDA 9400 is dedicated for application in high quality digital video
systems.
The figure below shows the generation of the internal H- and V-syncs in case of full CCIR 656
mode. The H656 sync is generated after the EAV. The V656 and F656 signals change
synchronously with the EAV timing reference code.
Explanation of 656 format
The figure below explains the functionality of the SYNCEN signal. The SDA 9400 needs the
SYNCEN (synchronization enable) signal, which is used to gate the YIN, UVIN as well as the HIN
and the VIN signal. This is implemented for front-ends which are working with 13.5 MHz and a large
FORMAT
HIN
VIN
YIN
UVIN
00
01 (CCIR 656 only
data)
10
11 (full CCIR 656)
PAL/NTSC
PAL/NTSC
PAL/NTSC
PAL/NTSC
4:2:2
CCIR 656
4:2:2
x
CCIR 656
x
CCIR 656
x
CCIR 656
CCIR 656
x
x
CLK1 (27 MHz)
u0
y0
v0
y1
u2
y3
YIN
CCIR 656 interface
SAV
EAV
288 Tclk1(PAL)
276 Tclk1(NTSC)
EAV
1728 Tclk1(PAL)
1716 Tclk1(NTSC)
EAV
x
x
EAV
x
x
SAV
x
CLK1 (27 MHz)
YIN
x
H656
V656
(e.g.)
F656
(e.g.)
EAV
11111111
00000000
00000000
1FV1P
3
P
2
P
1
P
0
SAV
11111111
00000000
00000000
1FV0P
3
P
2
P
1
P
0
F = 0 during field 1(A)
F = 1 during field 2(B)
V = 0 elsewhere
V = 1 during field blanking
MSB
LSB
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