參數(shù)資料
型號： SDA9257
廠商： SIEMENS A G
元件分類： 消費(fèi)家電
英文描述： Clock Sync Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PDIP28
文件頁數(shù)： 8/36頁
文件大小： 1304K
代理商： SDA9257
SDA 9257
Semiconductor Group
189
HPLL Control (subaddress 01)
*)
don’t care
Relationship between Horizontal Frequency
in CVBS and Frequency on CKL1
Control Bits
HPLL1
HPLL0
1728
0
*
)
1716
1
0
1536
1
1
Initiation of a Reset for HPLL
Control Bit RSTH
No function
0
HPLL is reset once, new lock-in process starts
1
Minimum Sync Pulse Length from which a Vertical Pulse is
Detected
26.6
μ
s
11.3
μ
s
Control Bit VTHRE
0
1
CVBS Clamping ON/OFF
Control Bit CLOF
Clamping ON
0
Clamping OFF
1
Selection of HPLL Lock-In Behavior
Control Bit VCRTV
Optimum for VCR
0
Optimum for CVBS from network
1
Freezing of the Actual Value of Clock Frequency
Control Bit FRZINC
No function
0
Instantaneous increment is freezing so that the instantaneous
frequency value is frozen and there is no lock-in function
of HPLL
1
Selection of Increment for Determining Clock Frequency
Increment from HPLL
Control Bit EXINC
0
Increment corresponding to
I
2
C Bus bits INC00 … INC15
(frequency generator mode)
1
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