參數(shù)資料
型號(hào)： SDA9257
廠商： SIEMENS A G
元件分類(lèi)： 消費(fèi)家電
英文描述： Clock Sync Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PDIP28
文件頁(yè)數(shù)： 3/36頁(yè)
文件大?。?/td> 1304K
代理商： SDA9257
SDA 9257
Semiconductor Group
184
When interference to CVBS is heavy, missing vertical pulses can be supplemented by switching on
the flywheel mode and vertical interference pulses can be eliminated by switching on the noise
suppression circuitry. Noise suppression and the flywheel mode can be enabled independently of
each other.
There is also the possibility of generating VS in the free-running mode. The VS pulses are then
completely independent of the vertical sync pulse in CVBS. When FREE = 1, a VS pulse is
generated every 262.5 or 312.5 lines (VF = 1 or 0 respectively). Free-running generation of VS
occurs every 262 or 312 lines in the terminal mode (TERM = 1).
The two fields can be identified by means of status bit HB. It toggles for every field but is set to 0
whenever the vertical pulse occurs within the first half of a line and within the noise-reduction
window (start of the first field).
3
Pulse Generation
The clock sync generator supplies the following pulses:
G
HS
G
VS
G
BLN
G
Two clamping pulses (H1 and H2)
G
Either a sandcastle (SC) or a super sandcastle (SSC) pulse or a composite sync (CS)
G
The HS pulse is 32 CLK1 clock periods long and can be shifted by the
I
2
C Bus in increments of
8 CLK1 clock periods each (
see timing diagram 1
).
G
For the VS pulse refer to vertical noise suppression
G
With the BLN pulse the start time (high-to-low edge) and the stop time (low-to-high edge) can be
set within a certain range of lines in increments of two CLK1 clock periods by the
I
2
C Bus. The
timing of BLN does not change during the field blanking interval.
G
The start time (low-to-high edge) and stop time can similarly be set in increments of two CLK1
clock periods for pulses H1 and H2.
G
The composite sync signal is derived from the CVBS, after it has passed through a low-pass
filter, by means of the sync threshold in the HPLL and is also provided with circuitry to suppress
noise which might occur due to very noisy CVBS (
refer to timing diagrams 4 and 5, and
diagram 1
).
G
An external transistor stage is required to generate sandcastle or super sandcastle pulses and
inserts the missing burst key in the pulse on the SC pin, which has only a zero, vertical- and
horizontal-blanking level. For this purpose the inverse burst-key signal is available at pin SINC
for triggering the transistor base (
refer to application circuit 6
).
The start time of the horizontal blanking level may be defined in increments of two CLK1 clock
periods over a wide range of lines by the
I
2
C Bus.
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