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參數(shù)資料
| 型號： | SDA9257 |
| 廠商： | SIEMENS A G |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Clock Sync Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP28 |
| 文件頁數(shù)： | 1/36頁 |
| 文件大?。?/td> | 1304K |
| 代理商： | SDA9257 |
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G
Multi-standard operation (50 Hz, 60 Hz; PAL, NTSC, SECAM)
G
Vertical noise suppression and 50/60-Hz detection
G
Serial digital output for actual frequency value and CVBS-black level
Applications
G
Memory based image improvement with analog color decoder
G
Memory based image improvement with digital multi-standard decoder
G
Free-running sync generator
G
Digital frequency synthesizer
Functional Description
The clock sync generator consists essentially of the following function blocks (
refer to block
diagram
):
G
Analog clamping
G
7-bit, 27-MHz A/D converter
G
Sync processor with digital horizontal PLL, vertical sync processor and pulse generator
G
Clock generator with discrete timing oscillator, D/A converter, analog PLL and divider, as well as
a crystal oscillator
G
I
2
C Bus interface
G
Button flutter elimination
Type
Ordering Code
Package
SDA 9257
Q67100-H5038
P-DIP-28-1
Clock Sync Generator
Preliminary Data
MOS IC
SDA 9257
P-DIP-28-1
Features
G
All settings made by
I
2
C Bus
G
PLL lock-in behavior can be set to TV- or VCR mode
G
Automatic clamping of CVBS input
G
Provides all horizontal and vertical sync signals and
clocks for operating PAMUX, analog color decoders,
the A/D converters, PSND and Featurebox
G
Free-running capability
G
Frequency generator function possible with digitally
adjustable frequency
G
Lock-in function of the PLL on CVBS also possible
with externally supplied 24-MHz or 27-MHz clock
Semiconductor Group
182
01.94
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