參數(shù)資料
型號： SDA9257
廠商： SIEMENS A G
元件分類： 消費(fèi)家電
英文描述： Clock Sync Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PDIP28
文件頁數(shù)： 7/36頁
文件大?。?/td> 1304K
代理商： SDA9257
SDA 9257
Semiconductor Group
188
*
Pin CLE should most definitely be connected to ground in this instance in order to minimize output signal jitter
Selection of Clock for Chip Operation
Control Bit SCLE
A line locked clock is generated by the internal PLL
0
Clock source is CLE. The radio between the horizontal
frequency in CVBS and CLK1 depends on control bits HPLL0
and HPLL1*
Clock Out Disable
Control Bit CLKDI
CKL1 and CKL2 tristate
1
CKL1 and CKL2 enabled
0
Selection of Function on SC and SINC
Control Bits
SC-Pin Function
SINC-Pin Function
SSC1
SSC0
Tristate
Tristate
0
0
Super sandcastle
without
burst
key
Burst key inverted
0
1
Sandcastle
1
1
Composite sync
Serial increment and
status bits
1
0
Level on
I
1
Control Bit
I
1
Low
0
High
1
Mode of Vertical Pulse Generation
Control Bit SCHW
No flywheel mode
0
Flywheel mode
1
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