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參數(shù)資料
| 型號： | SDA9257 |
| 廠商： | SIEMENS A G |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Clock Sync Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP28 |
| 文件頁數(shù)： | 15/36頁 |
| 文件大?。?/td> | 1304K |
| 代理商： | SDA9257 |
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SDA 9257
Semiconductor Group
196
Transmitter Format:
Status bit POR: POR is set by power on reset or by setting the bit RSTH.
POR is reset after reading the status byte.
Status Byte
Status Bits
KOI
THREUM FFGF
FF
HB
POR
POR
POR
Absolute Difference in Time between the
Horizontal Sync Pulse in CVBS and the HPLL
Status Bit KOI
Greater than or equal to 2.4
μ
s
Less than 2.4
μ
s
0
1
Absolute Difference in Time between the
Horizontal Sync Pulse in CVBS and the HPLL
Greater than 0.6
μ
s
Less than 0.6
μ
s for 8 or more successive lines
(i.e. HPLL well locked in)
Status Bit THRELIM
0
1
Identified Number of Lines per Field
(refer also to timing diagram 9)
Status Bits
Control Bit
VWW
FFGF
FF
Less than 287
0
1
×
×
1
Greater than or equal 287
0
0
Between 262 and 264
1
1
Between 312 and 314
1
0
1
Between 250 and 275
1
1
0
Between 300 and 325
1
0
0
Field Detection (Applicable to Interlace Only)
Status Bit HB
First field
0
Second field
1
S
1
A
A
P
Status Byte
Slave Address
N: no acknowledge
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