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參數(shù)資料
| 型號： | SDA9257 |
| 廠商： | SIEMENS A G |
| 元件分類： | 消費家電 |
| 英文描述： | Clock Sync Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP28 |
| 文件頁數(shù)： | 4/36頁 |
| 文件大?。?/td> | 1304K |
| 代理商： | SDA9257 |
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SDA 9257
Semiconductor Group
185
4
Miscellaneous Circuit Sections
G
To suppress bottom flutter in VCR mode, the frequency of the clock can be “hold” by “freezing”
the increment of the HPLL. The vertical-frequency “freezing-time” starts a number of lines
(programmable by the
I
2
C Bus) before the vertical pulse and then lasts for a number
(programmable) of lines (
refer to timing diagram 2
). The settings do not depend on
I
2
C-bit
VCRTV.
G
The increment of the HPLL, the black level and the status bits are output serially on the SINC pin
(optionally to the sandcastle pulse) and are therefore available for a digital color decoder, for
instance. Because the frame of these line-frequency output begins with a start bit (low) it can be
detected independently of the phase of HPLL (
refer also to timing diagram 3
).
G
An active low reset is available for other chips at pin RES. It is reset when the chip supply
V
DD
is
switched on or when voltage glitches occur in it. It is not cancelled until the crystal oscillator
resonates and the two device supplies
V
DD
and
V
DDA
are applied. The minimum length of time is
1 ms.
5
External Clock Mode of the HPPL
The HPPL locks onto the CVBS signal for the following operating ranges when the chip is operated
with a clock frequency supplied on pin CKE (SCLE bit at 1):
The jitter on output pulses HS, VS, BLN, H1 and H2 and output clocks CLK1 and CLK2 is several
CLK1-clock periods long.
Control Bit
Clock Frequency Range on CKE
HPPL 1
HPPL 0
0
X
26.1 … 27.9 MHz
1
0
26.1 … 27.9 MHz
1
1
23.1 … 24.9 MHz
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