- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98079 > SCANPSC100FDMQB (NATIONAL SEMICONDUCTOR CORP) SPECIALTY MICROPROCESSOR CIRCUIT, CDIP28 PDF資料下載
參數(shù)資料
| 型號： | SCANPSC100FDMQB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數(shù)： | 4/27頁 |
| 文件大小： | 381K |
| 代理商： | SCANPSC100FDMQB |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
Serial Scan Interface (SSI) (Continued)
to change only when SCK is low; therefore, TCK always
stops low. TCK does not toggle (remains low) under the
following conditions:
TDO Shifter/Buffer is enabled and empty.
TDO Shifter/Buffer is enabled in PRPG mode and is not
fully loaded.
TDI Shifter/Buffer is enabled and full.
TDI Shifter/Buffer is enabled in SSC mode but is not fully
loaded with an initial value.
TMS0 Shifter/Buffer is enabled and empty.
TMS1 Shifter/Buffer is enabled and empty.
CNT32 is enabled but not loaded.
CNT32 is enabled and has reached terminal count.
Also included within the TCK control block in CNT3, a 3-bit
count up counter. CNT3 is included to maintain byte align-
ment within the shifter/buffers by providing a signal to toggle
between the two 8-bit FIFOs which comprise the shifter/
buffer. The toggling operation occurs, in an enabled shifter/
buffer, each time CNT3 counts 8 TCK cycles or when CNT32
reaches terminal count. The CNT3 is reset to 0 when CNT32
reaches terminal count or after a PSC100 reset condition.
FREEZE MODE. This mode is included in the TCK control
block to support the 1149.1 SAMPLE operation. The intent of
the SAMPLE instruction is to allow device input and output
levels to be observed during normal system operation. Data
is latched (or “sampled”) into the boundary scan registers
when the TAP controller (see
Figure 8 on previous page)
transitions from the Capture-DR state to the Shift-DR state (if
SAMPLE/ PRELOAD is the active instruction). Synchroniz-
ing this “transition” (rising edge of TCK with TMS at logic low)
with a known system state is imperative to an accurate
pass/fail assessment. The Freeze Mode provides a means
of asynchronously creating the TCK pulse via an external
PSC100 pin. When the Freeze Pin Enable bit (bit 2 in Mode
Register 1) is set, a logic high on the PSC100 FRZ input pin
the Freeze Mode can be removed (i.e. Freeze Pin Enable bit
returned to logic 0 or Freeze pin forced low) and the sampled
data can be shifted out/evaluated using the “standard”
PSC100 protocol.
Figure 9 illustrates the logic implementa-
tion of the Freeze feature. It should be noted that Freeze
mode is simply gated with the TCK output and does not
disable shift operations within the shifter/buffers or disable
CNT32. Therefore, no shifting or TCK counting using CNT32
should be performed when Freeze mode is enabled.
The “standard” mode of TCK control uses CNT32 in conjunc-
tion with the status registers to start and stop TCK. For this
mode, CNT32 is enabled and loaded with the number of
TCK cycles required to shift the desired bits to/from the scan
chain. The shifter/buffer(s) participating in the shift operation
is enabled and provides the necessary full/empty status to
stop TCK for processor writes/reads. This mode of TCK
control provides a systematic protocol for managing PSC100
operations (specifically, handling partial bytes). Another op-
tion for TCK control relies solely on the status of the shifter/
buffers (i.e., CNT32 is disabled) to start and stop TCK. This
option eliminates the time required to load CNT32, but
makes management of partial bytes (see shifter/buffer de-
scription section) more cumbersome.
TMS(1:0) SHIFTER/BUFFERS
10032509
FIGURE 9. TCK Logic
10032510
FIGURE 10. TMS Shifter/Buffer Block Diagram
SCANPSC100F
Embedded
www.national.com
12
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SCANPSC100FLMQB | SPECIALTY MICROPROCESSOR CIRCUIT, CQCC28 |
| SCB68172C2F28 | VME BUS CONTROLLER, CDIP28 |
| SCC2691AC1D24 | 1 CHANNEL(S), 38.4K bps, SERIAL COMM CONTROLLER, PDSO24 |
| SCC2691AE1A28 | 1 CHANNEL(S), 38.4K bps, SERIAL COMM CONTROLLER, PQCC28 |
| SCC2692AC1A44-T | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCANPSC100FLMQB | 制造商:Texas Instruments 功能描述: |
| SCANPSC100FSC | 功能描述:接口 - 專用 Emb Boun Scan Cont RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANPSC100FSCX | 功能描述:接口 - 專用 Emb Boun Scan Cont RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANPSC110 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| SCANPSC110_ZFC3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。