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參數(shù)資料
| 型號： | SCANPSC100FDMQB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數(shù)： | 23/27頁 |
| 文件大小： | 381K |
| 代理商： | SCANPSC100FDMQB |
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Mode and Status Registers (Continued)
Bit 4: This bit enables the TMS0 shifter/buffer for shift operations. If this bit is set, the TMS0 shifter/buffer will cause TCK to stop
if it is empty.
Bit 3: This bit enables the TMS1 shifter/buffer for shift operations. If this bit is set, the TMS1 shifter/buffer will cause TCK to stop
if it is empty.
Bit 2: This bit is reserved and should remain as a logic 0 during all ’PSC100 operations.
Bit 1: If this bit is set, TMS will be forced high when the 32-bit counter is at state (00000001)h.
Bit 0: This bit causes TDI to be connected directly back through TDO for Loop-Around operations.
MODE REGISTER 1 (MODE1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TDO
TDI
CNT32
PRPG
SSC
Freeze
Test
Interrupt
Interrrupt
Interrupt
Enable
Pin
Loop-
Enable
Back
This register is purely a mode register. All bits are writeable and readable. The value 00000000 is placed in this register upon RST
low or a synchronous reset operation.
Bit 7:
If this bit is set and the TDO shifter/buffer is not full (i.e., one or both 8-bit TDO FIFOs are empty), the INT pin will
go high.
Bit 6:
If this bit is set and the TDI shifter/buffer is not empty (i.e., one or both 8-bit TDI FIFOs are full), the INT pin will
go high.
Bit 5:
If this bit is set, and the 32-bit counter is not loaded or has reached terminal count, the INT pin will go high.
Bit 4:
This bit signifies that the TD0 shifter/buffer is reconfigured as a 32-Bit Pseudo Random Pattern Generator. If set,
and MODE0 Bit 7 is set, the TDO shifter/buffer will stop TCK until a seed value has been written to all four of the
8-bit LFSR segments.
Bit 3:
This bit signifies that the TD1 shifter/buffer is reconfigured as a 16-Bit Serial Signature Compactor. If set, and
MODE0 Bit 6 is set, the TDI shifter/buffer will cause TCK to stop until a seed value has been written to the two
TDI registers.
Bit 2:
If this bit is set, a high value on FRZ will force TCK high (see TCK Control Section).
Bits 1 and 0: These bits are used to control Test Loop-Back operations according to the following table.
MODE1
Function
Bit 1
Bit 0
0
Normal Operation
0
1
Loop-Back TDO to TDI
MODE1
Function
Bit 1
Bit 0
1
0
Loop-Back TMS0 to TDI
1
Loop Back TMS1 to TDI
MODE REGISTER 2 (MODE2)
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Not
Continuous
Update
Single
Used
Update
Status
Reset
Step
CNT32
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TDO
TDI
CNT32
TMS0
TMS1
Continuous
Single
Status
Update
Reset
Step
CNT32
This register contains both mode and status bits. Bits 4–7 are status bits only. Bit 3 is a status bit during read operations and a
mode bit during write operations. Bits 0–2 are mode bits only. Upon RST low, or a synchronous reset, the value placed in MODE2
is 10111000 (Read mode). Latches used to update status bits 3–7 retain their last state upon RST and are in an “unknown” state
after power-up. To initialize the latches to a known state, they need to be updated using the Update Status bit (bit 2) or continuous
update bit (bit 3).
Bit 7: Set high if the TDO shifter/buffer is not full, i.e., one or both 8-bit TDO FIFOs are ready to be written to.
Bit 6: Set high if the TDI shifter/buffer is not empty, i.e., one or both 8-bit TDI FIFOs are ready to be read from.
SCANPSC100F
Embedded
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