參數(shù)資料
型號: SCANPSC100FDMQB
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, CDIP28
封裝: CERAMIC, DIP-28
文件頁數(shù): 26/27頁
文件大?。?/td> 381K
代理商: SCANPSC100FDMQB
TIMING WAVEFORMS (Continued)
Note 3:
Figures 4, 5: Figure 4 shows the best case bus cycle timing for SCK
and STB during consecutive read or write cycles. The rising edge of strobe
occurs a setup time, ts4 or before the falling edge of SCK. This allows the
cycle to be completed within 1.5 clock SCK clock cycles.
Figure 5 shows the
worst case bus cycle timing for SCK and STB during consecutive read or
write cycles. The rising edge of strobe does not meet the ts4 requirement
between STB and SCK. Therefore, the propagation of the internal PSC100
control and reset signals is delayed until the next falling edge of SCK. The
bus cycle is then completed 1.5 SCK cycles later creating a total bus cycle
time of 2.5 SCK cycles. If worst case timing is considered for bus cycle timing,
t s4 is not a mandatory timing specification.
10032505
FIGURE 4. Consecutive Read/Writes (best case timing)
10032506
FIGURE 5. Consecutive Read/Writes (worst case timing)
SCANPSC100F
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相關(guān)PDF資料
PDF描述
SCANPSC100FLMQB SPECIALTY MICROPROCESSOR CIRCUIT, CQCC28
SCB68172C2F28 VME BUS CONTROLLER, CDIP28
SCC2691AC1D24 1 CHANNEL(S), 38.4K bps, SERIAL COMM CONTROLLER, PDSO24
SCC2691AE1A28 1 CHANNEL(S), 38.4K bps, SERIAL COMM CONTROLLER, PQCC28
SCC2692AC1A44-T 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44
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