- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98079 > SCANPSC100FDMQB (NATIONAL SEMICONDUCTOR CORP) SPECIALTY MICROPROCESSOR CIRCUIT, CDIP28 PDF資料下載
參數(shù)資料
| 型號(hào)： | SCANPSC100FDMQB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數(shù)： | 16/27頁 |
| 文件大小： | 381K |
| 代理商： | SCANPSC100FDMQB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
Application Note
SCK MINIMUM PULSE WIDTH CALCULATION
The SCANPSC100 Parallel to Serial Converter is intended
to act as the interface between a processor and an IEEE
1149.1 boundary scan chain. When used in this configura-
tion, there is a critical timing situation that is not obvious.
This timing involves the system clock rate at which data from
the scan ring is being read into the ’PSC100’s TDI pin (target
TAP controllers in SHIFT-DR or SHIFT-IR states).
To fully understand the events which are taking place during
this critical period, it is useful to view the waveforms of
interest as they relate in time. See
Figure 16. The TCK is
derived internally to the ’PSC100 based on the system clock
(SCK) and clock gating control. The result is that when TCK
is running, it is at the same frequency as SCK but delayed in
time by the SCK-TCK propagation delay.
The TCK signal from the ’PSC100 drives all of the IEEE
1149.1 target devices. On the rising edge of TCK, data
present at each scan cell is clocked into it. On the falling
edge, this data is presented at the output of the same scan
cell for the next adjacent cell to read. With regards to the last
cell in a particular target, the falling edge of TCK presents
the data in the last scan cell to the TDO pin, a TCK-TDO
propagation delay later.
At the ’PSC100, data shifted in through the TDI pin is
clocked in on the rising edge of SCK, not TCK. The reason
for this is that TCK is generated internal to the ’PSC100 and
intended to control the boundary scan targets. The ’PSC100
is controlled by SCK, therefore the signal to be shifted into
the TDI pin needs to be referenced to SCK not TCK. New
TDI data must be present a TDI-SCK set-up time prior to the
rising edge of SCK in order to guarantee validity. Although
SCK is usually continuous, the TDI buffer is controlled by a
SHIFT-ENABLE signal which is generated internal to the
’PSC100, based on the status of the TDI buffer and the
Mode Registers.
We now see the three major timing components which limit
the duration of the SCK pulse width low. There are two minor
additional delays which should be noted. The TCK signal
from the ’PSC100 needs to arrive at the target device to be
recognized, and this takes a finite amount of time depending
on the signal trace length and impedance. Similarly, the TDO
signal of the last target in the chain needs to reach the TDI
pin of the ’PSC100, taking a finite amount of time as well.
These two trace delays can be minimized by making the
target device closest to the ’PSC100 the last device in the
chain. See
PROGRAMMING RESTRICTIONS
Because certain mode bits enable shift operations for certain
functions, these mode bits should not be changed when shift
operations are in progress. The alignment of all registers
during shift operations is controlled by a three bit counter in
the TCK control block. Enabling or disabling a function in the
middle of a shift operation may disrupt the logic necessary to
keep all shifter/buffers byte-aligned. For example, if the TDO
shifter/buffer (already loaded) is enabled while the three bit
counter value is three, the shifter/buffer will only shift out 5
bits of the first byte loaded.
The following bits should not be changed when shift opera-
tions are in progress, i.e., when TCK is enabled (see TCK
control section):
MODE0(7:3)
MODE1(4:3)
MODE2(0)
SCANPSC100F
Embedded
www.national.com
23
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SCANPSC100FLMQB | SPECIALTY MICROPROCESSOR CIRCUIT, CQCC28 |
| SCB68172C2F28 | VME BUS CONTROLLER, CDIP28 |
| SCC2691AC1D24 | 1 CHANNEL(S), 38.4K bps, SERIAL COMM CONTROLLER, PDSO24 |
| SCC2691AE1A28 | 1 CHANNEL(S), 38.4K bps, SERIAL COMM CONTROLLER, PQCC28 |
| SCC2692AC1A44-T | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCANPSC100FLMQB | 制造商:Texas Instruments 功能描述: |
| SCANPSC100FSC | 功能描述:接口 - 專用 Emb Boun Scan Cont RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANPSC100FSCX | 功能描述:接口 - 專用 Emb Boun Scan Cont RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANPSC110 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| SCANPSC110_ZFC3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。