參數(shù)資料
型號(hào)： SCANPSC100FDMQB
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, CDIP28
封裝： CERAMIC, DIP-28
文件頁(yè)數(shù)： 24/27頁(yè)
文件大小： 381K
代理商： SCANPSC100FDMQB
Mode and Status Registers (Continued)
Bit 5: Set high if the 32-bit counter has not been loaded, or has reached terminal count.
Bit 4: Set high if the TMS0 shifter/buffer is not full, i.e., one or both 8-bit TMS0 FIFOs are ready to be written to.
Bit 3 (Read Cycle):
Set high if the TMS1 shifter/buffer is not full, i.e., one or both 8-bit TMS1 FIFOs are ready to be written to.
Bit 3 (Write Cycle):
If set, will cause all status bits to be continuously updated.
Bit 2 (Read Cycle):
Shows the state of the Continuous Update bit during read operations (Bit 3 during writes).
Bit 2 (Write Cycle):
If set, will cause a pulse to be issued internally that will update all status bits. This bit will be reset upon completion of the
pulse. The state of this bit is not readable. It is reset upon RST low.
Bit 1: If set, will cause a synchronous reset of all functions except the parallel interface. The value of this bit will return to zero
when the reset operation is complete.
Bit 0: If set, will cause the 32-bit counter to count for one SCK cycle (no TCK cycle will be generated). The value of this bit will
return to zero when the single step operation is complete.
PROGRAMMING RESTRICTIONS
Because certain mode bits enable shift operations for certain functions, these mode bits should
not be changed when shift
operations are in progress. The alignment of all registers during shift operations is controlled by a 3-bit counter in the TCK control
block. Enabling or disabling a function in the middle of a shift operation may disrupt the logic necessary to keep all shifter/buffers
byte-aligned.
For example, if the TDO shifter/buffer (already loaded) is enabled while the 3-bit counter value is 3, the shifter/buffer will only shift
out only five bits of the first byte loaded.
The following bits should not be changed when shift operations are in progress, i.e., when TCK is enabled (see section on TCK
Control).
MODE0(7:3)
MODE1(4:3)
MODE2(0)
Parallel Processor Interface (PPI)
ADDRESS ASSIGNMENT
The following table defines which register is selected for
access with the address lines, A(2:0).
A2
A1
A0
R/W
Function
0
TDO Shifter/Buffer
0
1
Counter Register 1
0
1
0
TDI Shifter/Buffer
0
1
TDI Shifter/Buffer
0
1
0
TMS0 Shifter/Buffer
0
1
0
1
Counter Register 2
A2
A1
A0
R/W
Function
0
1
0
TMS1 Shifter/Buffer
0
1
Counter Register 3
1
0
32-Bit Counter
1
0
1
Counter Register 0
1
0
1
0
MODE0
1
0
1
MODE0
1
0
MODE1
1
0
1
MODE1
1
0
MODE2
1
MODE2
SCANPSC100F
Embedded
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相關(guān)PDF資料
PDF描述
SCANPSC100FLMQB SPECIALTY MICROPROCESSOR CIRCUIT, CQCC28
SCB68172C2F28 VME BUS CONTROLLER, CDIP28
SCC2691AC1D24 1 CHANNEL(S), 38.4K bps, SERIAL COMM CONTROLLER, PDSO24
SCC2691AE1A28 1 CHANNEL(S), 38.4K bps, SERIAL COMM CONTROLLER, PQCC28
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