參數(shù)資料
型號： SCANPSC100FDMQB
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, CDIP28
封裝： CERAMIC, DIP-28
文件頁數(shù)： 21/27頁
文件大?。?/td> 381K
代理商： SCANPSC100FDMQB
Pin Descriptions
Pin
Description
Name
RST (Input)
The Reset pin is an asynchronous input that, when low, initializes the ’PSC100. Mode bits, Shifter/Buffer
and CNT32 control logic, TCK Control, and the PPI are all initialized to defined states. RST has hysteresis
for improved noise immunity.
SCK (Input)
The System Clock drives all internal timing. The test clock, TCK, is a gated and buffered version of SCK.
SCK has hysteresis for improved immunity.
OE (Input)
Output Enable TRI-STATEs all SSI outputs when high. A 20 k
pull-up resistor is connected to
automatically TRI-STATE these outputs when this signal is floating.
CE (Input)
Chip Enable, when low, enables the PPI for byte transfers. D(7:0) and RDY are TRI-STATEd if CE is high.
CE has hysteresis for improved noise immunity.
R/W (Input)
Read/Write defines a PPI cycle — Read when high, Write when low. R/ W has hysteresis for improved noise
immunity.
STB (Input)
Strobe is used for timing all PPI byte transfers. D(7:0) are TRI-STATEd when STB is high. All other PPI
inputs must meet specified setup and hold times with respect to this signal. STB has hysteresis for
improved noise immunity.
A(2:0)
The Address pins are used to select the register to be written to or read from.
(Input)
D(7:0) (I/O)
Bidirectional pins used to transfer parallel data to and from the ’PSC100.
INT
Interrupt is used to trigger a host interrupt for any of the defined interrupt events. INT is active high.
(Output)
RDY
Ready is used to synchronize asynchronous byte transfers between the host and the ’PSC100. When low,
(TRI-STATE
RDY signals that the addressed register is ready to be accessed RDY is enabled when CE is low.
Output)
TDO
Test Data Out is the serial scan output from the ’PSC100. TDO is enabled when OE is low.
(TRI-STATE
Output)
TMS(1:0)
The Test Mode Select pins are serial outputs used to supply control logic to the UUT. TMS(1:0) are
(TRI-STATE
enabled when OE is low.
Output)
TCK
The Test Clock output is a buffered version of SCK for distribution in the UUT. TCK Control logic starts
(TRI-STATE
and stops TCK to prevent overflow and underflow conditions. TCK is enabled when OE is low.
Output)
TDI (Input)
Test Data In is the serial scan input to the ’PSC100. A 20 k
pull-up resistor is connected to force TDI to a
logic 1 when the TDO line from the UUT is floating.
FRZ (Input)
The Freeze pin is used to asynchronously generate a user-specific pulse on TCK. If the FRZ Enable Mode
bit is set, TCK will be forced high if FRZ goes high. FRZ has hysteresis for improved noise immunity.
SCANPSC100F
Embedded
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