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參數(shù)資料
| 型號： | SCANPSC100F |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Embedded Boundary Scan Controller(嵌入式邊界掃描控制器) |
| 中文描述： | 嵌入式邊界掃描控制器（嵌入式邊界掃描控制器） |
| 文件頁數(shù)： | 9/25頁 |
| 文件大?。?/td> | 364K |
| 代理商： | SCANPSC100F |
Parallel Processor Interface (PPI)
(Continued)
dynamic memories. Holding the local bus with the PSC100F
RDY line long enough to violate a DRAM refresh time will re-
sult in lost data within the dynamic memory.
Writing and Reading without the use of RDY :
With use of
worst case PSC100F timing, Write and Read cycles can be
successfully completed without the use of the RDY signal.All
read and write cycles will complete within 2.5 SCK cycles
(worst case). Therefore, by assuring at least 2.5 cycles occur
after the rising edge of STB, bus cycles can be completed
without using the RDY “handshake”. The critical timing rela-
tionship within the PSC100F for write and read operation is
between the rising edge of STB and the falling edge of SCK.
The rising edge of strobe latches the address/data and also
generates the internal signals required to complete read/
write within the PSC100F (including a signal with resets the
read/write logic and releases the RDY line). The propagation
of these internal signals is initiated on the first falling edge of
SCK after the STB pin is asserted high. If the rising edge on
STB occurs an internal setup time (t
) or greater before the
falling edge of SCK, the bus cycle can be completed within
1.5 SCK cycles (see Figure 4). However, if the internal setup
time is not met, the propagation of internal control/reset sig-
nals is delayed until the next falling edge of SCK (1 SCK
cycle later) which effectively completes the read/write opera-
tion and reset the logic for the next bus cycle within 2.5
cycles (see Figure 5). Synchronizing the rising edge of STB
with the falling edge of SCK to assure that t
is met provides
the maximum performance for a read/write operation. How-
ever, the asynchronous interface can be used effectively with
software delays, hardware delays or programmed wait
states (to assure 2.5 SCK cycles are completed) to avoid the
need for synchronization.
Consecutive Reads and Writes:
Separate control logic and
data/address latches are used for a read and write operation
within the PSC100F. This allows a write to occur after a read
(or conversely, a read to occur after a write) prior to the 1.5/
2.5 SCK clock cycle requirements described above. The tim-
ing for a read (or write) followed by a write (or read) is shown
in Figure 5 and Figure 6
SYNCHRONIZATION
Writes and reads can be synchronized by using any of three
methods: polling, interrupts, or wait state generation:
Status bits may be polled to see if a register is ready to be
written to or read from. To stabilize the status bits for read
operations, the Update Status bit must be set in MODE2
to latch the status.
Note:
The status bits only provide the state of the shifter/buffers and do not
indicate that an internal write or read is complete. Therefore, for appli-
cations not using the RDY signal to monitor the internal write/read sta-
tus, timing must be controlled to assure that at least 2.5 SCK cycles
are completed between consecutive read or consecutive write cycles.
Any of three different events can be used to generate in-
terrupts by forcing the INT pin high, see Table 1
The RDY pin can be used to hold off the host until the ad-
dressed register is ready to be accessed. As described
above, this pin can also be used to hold off additional
reads/writes until the synchronizer has recovered from
the previous read/write. RDY = 0 signifies that the
’PSC100F is ready to complete the current PPI cycle.
The logic that determines the state of RDY is summa-
rized in Table 2
Reading from CNT32 can be synchronized for testing by us-
ing the Single Step Counter mode bit.
TABLE 1. Interrupt Logic
MODE1(7) = 1 and TDO
Shifter/Buffer Not Full
MODE1(6) = 1 and TDI
Shifter/Buffer Not Empty
MODE1(5) = 1 and
CNT32 Not Loaded, or at
Terminal Count
X
X
1
0
INT
1
X
X
0
X
1
X
0
1
1
1
0
Note 6:
Interrupts are generated using the INT pin. Three events trigger INT high. Each event has its own mode bit associated with it for masking or enabling these
interrupts.
www.national.com
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