- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376340 > SCANPSC100F (National Semiconductor Corporation) Embedded Boundary Scan Controller(嵌入式邊界掃描控制器) PDF資料下載
參數(shù)資料
| 型號(hào)： | SCANPSC100F |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Embedded Boundary Scan Controller(嵌入式邊界掃描控制器) |
| 中文描述： | 嵌入式邊界掃描控制器（嵌入式邊界掃描控制器） |
| 文件頁數(shù)： | 3/25頁 |
| 文件大?。?/td> | 364K |
| 代理商： | SCANPSC100F |
Pin Descriptions
(Continued)
Pin
Name
CE
(Input)
Description
Chip Enable, when low, enables the PPI for byte transfers. D(7:0) and RDY are TRI-STATEd if CE is high.
CE has hysteresis for improved noise immunity.
Read/Write defines a PPI cycle— Read when high, Write when low. R/ W has hysteresis for improved
noise immunity.
Strobe is used for timing all PPI byte transfers. D(7:0) are TRI-STATEd when STB is high. All other PPI
inputs must meet specified setup and hold times with respect to this signal. STB has hysteresis for
improved noise immunity.
The Address pins are used to select the register to be written to or read from.
R/W
(Input)
STB
(Input)
A(2:0)
(Input)
D(7:0) (I/O)
INT
(Output)
RDY
(TRI-STATE
Output)
TDO
(TRI-STATE
Output)
TMS(1:0)
(TRI-STATE
Output)
TCK
(TRI-STATE
Output)
TDI
(Input)
Bidirectional pins used to transfer parallel data to and from the ’PSC100.
Interrupt is used to trigger a host interrupt for any of the defined interrupt events. INT is active high.
Ready is used to synchronize asynchronous byte transfers between the host and the ’PSC100. When low,
RDY signals that the addressed register is ready to be accessed RDY is enabled when CE is low.
Test Data Out is the serial scan output from the ’PSC100. TDO is enabled when OE is low.
The Test Mode Select pins are serial outputs used to supply control logic to the UUT. TMS(1:0) are
enabled when OE is low.
The Test Clock output is a buffered version of SCK for distribution in the UUT. TCK Control logic starts
and stops TCK to prevent overflow and underflow conditions. TCK is enabled when OE is low.
Test Data In is the serial scan input to the ’PSC100. A 20 k
pull-up resistor is connected to force TDI to
a logic 1 when the TDO line from the UUT is floating.
The Freeze pin is used to asynchronously generate a user-specific pulse on TCK. If the FRZ Enable Mode
bit is set, TCK will be forced high if FRZ goes high. FRZ has hysteresis for improved noise immunity.
FRZ
(Input)
Mode and Status Registers
MODE REGISTER 0 (MODE0)
Bit 7
TDO
Enable
Bit 6
TDI
Enable
Bit 5
CNT32
Enable
Bit 4
TMS0
Enable
Bit 3
TMS1
Enable
Bit 2
Bit 1
Bit 0
Loop-
Around
Enable
Auto TMS High
Enable
Reserved
This register is purely a mode register. All bits are writeable
and readable. The value 00100000 is placed in this register
upon RST low or a synchronous reset operation.
Bit 7: This bit enables the TDO shifter/buffer for shift op-
erations. If this bit is set, the TDO shifter/buffer will
cause TCK to stop if it is empty.
Bit 6: This bit enables the TDI shifter/buffer for shift op-
erations. If this bit is set, the TDI shifter/buffer will
cause TCK to stop if it is full.
Bit 5: This bit enables the 32-bit counter. If this bit is set,
the counter will cause TCK to stop if if has not been
loaded or if it has reached terminal count.
Bit 4: This bit enables the TMS0 shifter/buffer for shift op-
erations. If this bit is set, the TMS0 shifter/buffer will
cause TCK to stop if it is empty.
Bit 3: This bit enables the TMS1 shifter/buffer for shift op-
erations. If this bit is set, the TMS1 shifter/buffer will
cause TCK to stop if it is empty.
Bit 2: This bit is reserved and should remain as a logic 0
during all ’PSC100 operations.
Bit 1: If this bit is set, TMS will be forced high when the
32-bit counter is at state (00000001)h.
Bit 0: This bit causes TDI to be connected directly back
through TDO for Loop-Around operations.
www.national.com
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SCANPSC110F | SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port(掃描橋分層多點(diǎn)可設(shè)定地址的JTAG端口) |
| SCANPSC110 | SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| SCANPSC110FDMQB | SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| SCANPSC110FFMQB | SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| SCANPSC110FLMQB | SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCANPSC100FLMQB | 制造商:Texas Instruments 功能描述: |
| SCANPSC100FSC | 功能描述:接口 - 專用 Emb Boun Scan Cont RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANPSC100FSCX | 功能描述:接口 - 專用 Emb Boun Scan Cont RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANPSC110 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| SCANPSC110_ZFC3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。