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參數(shù)資料
| 型號： | SCANPSC100F |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Embedded Boundary Scan Controller(嵌入式邊界掃描控制器) |
| 中文描述： | 嵌入式邊界掃描控制器（嵌入式邊界掃描控制器） |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 364K |
| 代理商： | SCANPSC100F |
Parallel Processor Interface (PPI)
(Continued)
TIMING WAVEFORMS (Continued)
Note 4:
Figures 6, 7 This diagram shows the timing for a read followed by a write (or write followed by a read). Separate Read and Write data/address latches and
control logic allow consecutive read/write or write/read operations to be overlapped (i.e., do not need to wait 2 or 3 SCK cycles between bus cycles). For the best
case timing scenario (Figure 6 rising edge of STB to falling edge of SCK greater than t
), a new bus cycle can be performed each SCK cycle. For the worst timing
scenario (Figure 7 rising edge of STB to falling edge of SCK is less than t
s4
), a one SCK cycle delay must be included after each back to back read/write or write/
read sequence.
Note 5:
Figures 4, 5, 6, 7assume that the PSC100 register participating in the bus cycle is ready to accept/provide data. For bus cycles involving a PSC100 shifter/
buffer(s), the ready status of a shifter/buffer can be checked using the status bits in Mode Register 2 prior to the start of the bus cycle. Polling is required when the
RDY pin is not used to provide a processor “handshake”.
READ AND WRITE CYCLES
A
Write cycle
(see Figure 2) is initiated by asserting CE and
R/W low followed by a low on STB a set time later. CE and
STB are gated within the PSC100F and may be asserted
concurrently (i.e., zero setup and hold time). The address is
then asserted on A2:0 to indicate which internal address
within the PSC100F will be written to by the processor. An
address decoder within the PSC100F monitors the address
lines for a valid PSC100F register address. Once a valid ad-
dress has been decoded, the RDY line becomes active (a
propagation delay time later). The active RDY line will go low
immediately if the addressed register is ready to accept data.
If the addressed register is not ready, the RDY pin will re-
main high preventing the processor from completing the bus
cycle. Once the register is ready to receive date (see Table
2), the RDY pin will go low and processor can resume the
write cycle. The processor then forces a high on STB (a wait
time after RDY goes low) which latches the address (A2:0)
and data (D7:0) completing the bus cycle. The RDY line is
forced high a propagation delay later.
A
Read cycle
(see Figure 3) is initiated by asserting CE low
and R/W high followed by a low on STB a set time later. CE
and STB are gated within the PSC100F and may be as-
serted concurrently (i.e., zero setup and hold time). The ad-
dress bits (A2:0) are then asserted to indicate which internal
address within the PSC100F will be read by the processor.
An address decoder within the PSC100F monitors the ad-
dress lines for a valid PSC100F register address. Once a
valid address has been decoded and if the addressed
PSC100F register is ready to be read (see Table 2), valid
data is placed on the Data lines (D7:0) a propagation delay
later and the ready line is asserted low. If the addressed reg-
ister is not ready (e.g., the TDI shifter/buffer is empty), the
ready line will remain high and hold the bus cycle until the
register contains valid data. RDY will then go low allowing
the read cycle to continue. With the high to low edge on RDY
line, the processor can successfully read the valid data.
However, the bus cycle is not completed within the PSC100F
until the rising edge on STB which resets the PSC100F read
logic (required prior to the start of the next read cycle).
Important note concerning the use of RDY :
The RDY sig-
nal provides a useful “handshake” between the PSC100F
and the processor. However, care must be taken when using
the PSC100F RDY signal to prevent a large (or indefinite)
number of processor generated wait states. For example, if
the TDO shifter/buffer is not enabled for shift operations and
the processor writes to the TDO shifter/buffer address 3
times, the two registers which make up the TDO shifter/
buffer will accept the first two bytes of data, but since the
data is not shifting out, the 3rd byte will be held off by the
RDY signal indefinitely. An equally severe problem could re-
sult with a finite number of wait states if the application uses
DS100325-20
FIGURE 6. Read/Write or Write/Read (best case timing)
DS100325-7
FIGURE 7. Read/Write or Write/Read (worst case timing)
www.national.com
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