- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376340 > SCANPSC100F (National Semiconductor Corporation) Embedded Boundary Scan Controller(嵌入式邊界掃描控制器) PDF資料下載
參數(shù)資料
| 型號： | SCANPSC100F |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Embedded Boundary Scan Controller(嵌入式邊界掃描控制器) |
| 中文描述： | 嵌入式邊界掃描控制器（嵌入式邊界掃描控制器） |
| 文件頁數(shù)： | 5/25頁 |
| 文件大小： | 364K |
| 代理商： | SCANPSC100F |
Mode and Status Registers
(Continued)
Bit 2
(Write Cycle):
If set, will cause a pulse to be issued internally that
will update all status bits. This bit will be reset upon
completion of the pulse. The state of this bit is not
readable. It is reset upon RST low.
Bit 1: If set, will cause a synchronous reset of all func-
tions except the parallel interface. The value of this
bit will return to zero when the reset operation is
complete.
Bit 0: If set, will cause the 32-bit counter to count for one
SCK cycle (no TCK cycle will be generated). The
value of this bit will return to zero when the single
step operation is complete.
PROGRAMMING RESTRICTIONS
Because certain mode bits enable shift operations for certain
functions, these mode bits should notbe changed when shift
operations are in progress. The alignment of all registers
during shift operations is controlled by a 3-bit counter in the
TCK control block. Enabling or disabling a function in the
middle of a shift operation may disrupt the logic necessary to
keep all shifter/buffers byte-aligned.
For example, if the TDO shifter/buffer (already loaded) is en-
abled while the 3-bit counter value is 3, the shifter/buffer will
only shift out only five bits of the first byte loaded.
The following bits should not be changed when shift opera-
tions are in progress, i.e., when TCK is enabled (see section
on TCK Control).
MODE0(7:3)
MODE1(4:3)
MODE2(0)
Parallel Processor Interface (PPI)
ADDRESS ASSIGNMENT
The following table defines which register is selected for ac-
cess with the address lines, A(2:0).
A2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R/W
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Function
TDO Shifter/Buffer
Counter Register 1
TDI Shifter/Buffer
TDI Shifter/Buffer
TMS0 Shifter/Buffer
Counter Register 2
TMS1 Shifter/Buffer
Counter Register 3
32-Bit Counter
Counter Register 0
MODE0
MODE0
MODE1
MODE1
MODE2
MODE2
www.national.com
5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SCANPSC110F | SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port(掃描橋分層多點可設(shè)定地址的JTAG端口) |
| SCANPSC110 | SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| SCANPSC110FDMQB | SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| SCANPSC110FFMQB | SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| SCANPSC110FLMQB | SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCANPSC100FLMQB | 制造商:Texas Instruments 功能描述: |
| SCANPSC100FSC | 功能描述:接口 - 專用 Emb Boun Scan Cont RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANPSC100FSCX | 功能描述:接口 - 專用 Emb Boun Scan Cont RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANPSC110 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| SCANPSC110_ZFC3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。