參數(shù)資料
型號： SCANPSC100F
廠商： National Semiconductor Corporation
英文描述： Embedded Boundary Scan Controller(嵌入式邊界掃描控制器)
中文描述： 嵌入式邊界掃描控制器（嵌入式邊界掃描控制器）
文件頁數(shù)： 4/25頁
文件大?。?/td> 364K
代理商： SCANPSC100F
Mode and Status Registers
(Continued)
MODE REGISTER 1 (MODE1)
Bit 7
TDO
Interrupt
Enable
Bit 6
TDI
Interrrupt
Enable
Bit 5
CNT32
Interrupt
Enable
Bit 4
PRPG
Enable
Bit 3
SSC
Enable
Bit 2
Freeze
Pin
Enable
Bit 1
Test
Loop-
Back
Bit 0
Test
Loop-
Back
This register is purely a mode register. All bits are writeable
and readable. The value 00000000 is placed in this register
upon RST low or a synchronous reset operation.
Bit 7:
If this bit is set and the TDO shifter/buffer is
not full (i.e., one or both 8-bit TDO FIFOs
are empty), the INT pin will go high.
Bit 6:
If this bit is set and the TDI shifter/buffer is
not empty (i.e., one or both 8-bit TDI FIFOs
are full), the INT pin will go high.
Bit 5:
If this bit is set, and the 32-bit counter is not
loaded or has reached terminal count, the
INT pin will go high.
Bit 4:
This bit signifies that the TD0 shifter/buffer
is reconfigured as a 32-Bit Pseudo Random
Pattern Generator. If set, and MODE0 Bit 7
is set, the TDO shifter/buffer will stop TCK
until a seed value has been written to all
four of the 8-bit LFSR segments.
Bit 3:
This bit signifies that the TD1 shifter/buffer
is reconfigured as a 16-Bit Serial Signature
Compactor. If set, and MODE0 Bit 6 is set,
the TDI shifter/buffer will cause TCK to stop
until a seed value has been written to the
two TDI registers.
If this bit is set, a high value on FRZ will
force TCK high (see TCK Control Section).
Bits 1 and 0: These
bits
Test Loop-Back operations according to the
following table.
Bit 2:
are
used
to
control
MODE1
Bit 1
0
0
1
1
MODE1
Bit 0
0
1
0
1
Function
Normal Operation
Loop-Back TDO to TDI
Loop-Back TMS0 to TDI
Loop Back TMS1 to TDI
MODE REGISTER 2 (MODE2)
Write:
Bit 7
Not
Used
Bit 6
Not
Used
Bit 5
Not
Used
Bit 4
Not
Used
Bit 3
Bit 2
Update
Status
Bit 1
Bit 0
Single
Step
CNT32
Continuous
Update
Reset
Read:
Bit 7
TDO
Status
Bit 6
TDI
Status
Bit 5
CNT32
Status
Bit 4
TMS0
Status
Bit 3
TMS1
Status
Bit 2
Bit 1
Bit 0
Single
Step
CNT32
Continuous
Update
Reset
This register contains both mode and status bits. Bits 4–7
are status bits only. Bit 3 is a status bit during read opera-
tions and a mode bit during write operations. Bits 0–2 are
mode bits only. Upon RST low, or a synchronous reset, the
value placed in MODE2 is 10111000 (Read mode). Latches
used to update status bits 3–7 retain their last state upon
RST and are in an “unknown” state after power-up. To initial-
ize the latches to a known state, they need to be updated us-
ing the Update Status bit (bit 2) or continuous update bit (bit
3).
Bit 7: Set high if the TDO shifter/buffer is not full, i.e., one
or both 8-bit TDO FIFOs are ready to be written to.
Bit 6: Set high if the TDI shifter/buffer is not empty, i.e.,
one or both 8-bit TDI FIFOs are ready to be read
from.
Bit 5: Set high if the 32-bit counter has not been loaded,
or has reached terminal count.
Bit 4: Set high if the TMS0 shifter/buffer is not full, i.e.,
one or both 8-bit TMS0 FIFOs are ready to be writ-
ten to.
Bit 3
(Read Cycle):
Set high if the TMS1 shifter/buffer is not full, i.e.,
one or both 8-bit TMS1 FIFOs are ready to be writ-
ten to.
Bit 3
(Write Cycle):
If set, will cause all status bits to be continuously
updated.
Bit 2
(Read Cycle):
Shows the state of the Continuous Update bit dur-
ing read operations (Bit 3 during writes).
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