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參數(shù)資料
| 型號： | SCANPSC100F |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Embedded Boundary Scan Controller(嵌入式邊界掃描控制器) |
| 中文描述： | 嵌入式邊界掃描控制器（嵌入式邊界掃描控制器） |
| 文件頁數(shù)： | 2/25頁 |
| 文件大?。?/td> | 364K |
| 代理商： | SCANPSC100F |
Chip Architecture
The ’PSC100 is designed to act together with a parallel bus
host as a serial test bus master. Parallel data is written by the
host to the ’PSC100, which serializes the data for application
to a serial test bus. Serial data returning from the target scan
chain(s) is placed on the processor port for parallel reads.
Several features are included in the ’PSC100 which make
scan test communication more convenient and efficient.
Figure 1 shows the major functional blocks of the ’PSC100
design. The Parallel Processor Interface (PPI) is an asyn-
chronous, 8-bit parallel interface which is used by the host
processor to write and read data. The PPI generates the
necessary internal data, address, and control signals to
complete internal write and read operations.
The Serial Scan Interface (SSI) consists of a bank of
double-buffered parallel/serial shift registers (i.e., a 2 x 8 bit
FIFO), or Shifter/Buffers. The double buffering improves effi-
ciency by allowing parallel writes or reads to/from one of the
two 8-bit FIFOs within the shifter/buffer while the other FIFO
is shifting data to/from the scan chain. Three Shifter/Buffers
are provided for outgoing serial data and one for incoming
serial data. Test Data Out (TDO) is for scanning out test data
while the two Test Mode Select signals (TMS0/1) are used to
provide user specific control data. Test Data In (TDI) re-
ceives serial data from the scan chain. A local control block
is associated with each Shifter/Buffer to provide shift and
load control as well as providing full or empty status. The SSI
also provides Test Clock (TCK) Control. TCK is stopped and
started depending on the status of the Shifter/Buffers or the
32-bit Counter. By stopping and starting TCK, scan opera-
tions will proceed only when the enabled Shifter/Buffers are
ready to send and/or receive serial data.
The 32-bit Counter (CNT32) is a count-down binary counter
included to assist in controlling the SSI. The initial state of
CNT32 is loaded from the parallel port with four consecutive
writes to its address. When enabled, CNT32 is used to pro-
gram the number of TCKs applied by the SSI to the bound-
ary scan chain(s). The value of CNT32 can also be used to
generate interrupts (i.e., when CNT32 reaches terminal
count) and to trigger ’PSC100 features, such as, Auto TMS
High (discussed later within this datasheet).
The Mode and Status Registers are used to control and ob-
serve the operation of the SSI and CNT32. Each of the
Shifter/Buffers and CNT32 have an associated mode bit
which enables it for participation in on-going operations. Sta-
tus bits can be used for polling operations.
Pin Descriptions
Pin
Name
RST
(Input)
Description
The Reset pin is an asynchronous input that, when low, initializes the ’PSC100. Mode bits, Shifter/Buffer
and CNT32 control logic, TCK Control, and the PPI are all initialized to defined states. RST has hysteresis
for improved noise immunity.
The System Clock drives all internal timing. The test clock, TCK, is a gated and buffered version of SCK.
SCK has hysteresis for improved immunity.
Output Enable TRI-STATEs all SSI outputs when high. A 20 k
pull-up resistor is connected to
automatically TRI-STATE
these outputs when this signal is floating.
SCK
(Input)
OE
(Input)
DS100325-2
FIGURE 1. ’PSC100 Block Diagram
www.national.com
2
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