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參數(shù)資料
| 型號： | SCANPSC100F |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Embedded Boundary Scan Controller(嵌入式邊界掃描控制器) |
| 中文描述： | 嵌入式邊界掃描控制器（嵌入式邊界掃描控制器） |
| 文件頁數(shù)： | 16/25頁 |
| 文件大?。?/td> | 364K |
| 代理商： | SCANPSC100F |
Serial Scan Interface (SSI)
(Continued)
is loaded sequentially, most significant byte first, least signifi-
cant byte last. When in SSC mode, writes can be completed
at any time; however, shift operations will be disabled until
the SSC is fully loaded. PPI reads from TDI are ignored while
in SSC mode.
Upon leaving SSC mode an internal pulse causes the TDI
shifter/buffer to be full. Also, local read select logic is initial-
ized such that the signature is read most-significant byte
first.
TEST LOOP-BACK MODES
. This feature provides a means
for testing ’PSC100 functionality by looping data appearing
at the output of an outgoing shifter/buffer (i.e., TMS0, TMS1
or TDO) back to the input of the TDI shifter/buffer. The loop
back function is accomplished with a simple multiplexer (see
Figure 13) whose path selection is determined by setting the
mode bits in MODE1(1:0). Loop back does not disable TCK
or prevent shifting of data in the shifter/buffers to the scan
chain(s) connected to the PSC100. Therefore, the state and
operation of the TAP controllers within the scan chain(s)
must be considered when developing Loop-Back test vec-
tors to prevent undesired shifting of data or TAP controller
transitions within the scan chain.
32-BIT COUNTER (CNT32)
CNT32 is a 32-bit, count-down binary counter arranged in
four 8-bit segments. CNT32 can be loaded independent of
its enable/disable status. Loading requires four consecutive
writes to its address (least significant byte first). These four
writes must not be interleaved with writes to any other ad-
dress or the CNT32 write control logic will be re-initialized.
This re-initialization will result in a partially filled counter with
an undesired value CNT32 is reset each time the counter
hits terminal count or by asserting the RST pin. A synchro-
nous reset condition (setting Mode2(1)) does not reset the
counter and a new value must be written to CNT32 to pro-
vide the desired number of TCK cycles.
SINGLE STEP MODE
: All four 8-bit registers are readable
for testability; however, there are no update latches similar to
the ones used for the status bits. To stabilize the counter for
read operations during on-board test, the Single Step Mode
has been added. This allows the user to place CNT32 in any
state and then count for one SCK cycle (TCK will not toggle
when in singled step mode). The result can then be read
from the PPI. The counter can be tested by loading it with
values at its boundary conditions, and then clocking for one
cycle to see the results. For example, the counter could be
loaded with the value:
00000001
00000000
00000000
The next step is to set the Single Step Mode bit so that the
counter counts down to the next state and stops. The next
value is:
00000000
11111111
11111111
Four read cycles using the PPI will reveal the results of the
test.
Note:
CNT32 will not wrap from terminal count (i.e., 00000000h decremented
by 1 will remain unchanged and will not wrap to FFFFFFFFh). There-
fore, CNT32 should be loaded with a non-zero value prior to a Single
Step Mode Operation.
00000000
11111111
TIMING WAVEFORMS
DS100325-15
FIGURE 15. Serial Scan Interface Timing
www.national.com
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