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Chapter 13 FlexRay Communication Controller (FLEXRAY)
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
465
13.4.3
PLL Lock Handling
For correct exray bus functionality of the protocol engine, it is required that the PLL in the CGMIPLL
module is locked while the protocol engine is driving data onto the exray bus. The lock state of the PLL
The FlexRay block drives its FlexRay transmit enable ports TXE_A and TXE_B to active state only if the
UNLOCKF is 1, the FlexRay block drives its FlexRay transmit enable ports TXE_A and TXE_B to its
inactive state 1.
13.4.3.1
PLL Loss of Lock
If the PLL goes from the locked state to the unlock state, the CGMIPLL module sets the lock bit LOCK
to 0 and the unlock ag UNLOCKF to 1. As a result, the FlexRay block drives its FlexRay transmit enable
ports TXE_A and TXE_B to its inactive states 1 and thus stops the transmission onto the FlexRay bus
immediately. As a result of the loss of lock, the correct operation of the PE is no longer guaranteed. The
application should perform a shutdown of the FlexRay module as described in
13.7.2, “Shut Down13.4.3.2
PLL Gain of Lock
If the PLL goes from the unlocked state to the locked state, the CGMIPLL module sets the lock bit LOCK
to 1. The unlock ag UNLOCKF is not cleared by the module, this has to be done by the application. After
the clearing of the unlock ag UNLOCKF, the application can perform the FlexRay initialization as
13.5
Memory Map and Register Description
The FlexRay block occupies 512 bytes of address space starting atthe FlexRay block’s base address
dened by the memory map of the MCU.
13.5.1
Memory Map
The complete memory map of the FlexRay block is shown in
Table 13-3. The addresses presented here are
the offsets relative to the FlexRay block base address which is dened by the MCU address map.
Table 13-3. FlexRay Memory Map (Sheet 1 of 4)
Offset
Register
Access
Module Conguration and Control
0x0000
R
0x0002
R/W
0x0004
R/W
0x0006
R/W
0x0008
R/W
0x000A
R/W