
Chapter 3 Voltage Regulator (S12VREGL3V3V1)
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
119
3.3.2
Register Descriptions
This section describes all the VREG_3V3 registers and their individual bits.
3.3.2.1
HT Control Register (VREGHTCL)
3.3.2.2
Control Register (VREGCTRL)
The VREGCTRL register allows the conguration of the VREG_3V3 low-voltage detect features.
0x02F0
76543210
R0
0
VSEL
VAE
HTEN
HTDS
HTIE
HTIF
W
Reset
0
10000
= Unimplemented or Reserved
Table 3-4. VREGHTCL Field Descriptions
Field
Description
7, 6
Reserved
These reserved bits are used for test purposes and writable only in special modes.
They must remain clear for correct temperature sensor operation.
5
VSEL
Voltage Access Select Bit — If set, the bandgap reference voltage VBG can be accessed internally (i.e.
multiplexed to an internal Analog to Digital Converter channel). . The internal access must be enabled by bit
VAE. See device level specication for connectivity.
0 An internal voltage can be accessed internally if VAE is set.
1 Bandgap reference voltage VBG can be accessed internally if VAE is set.
4
VAE
Voltage Access Enable Bit — If set, the voltage selected by bit VSEL can be accessed internally (i.e.
multiplexed to an internal Analog to Digital Converter channel). See device level specication for connectivity.
0 Voltage selected by VSEL can not be accessed internally (i.e. External analog input is connected to Analog
to Digital Converter channel).
1 Voltage selected by VSEL can be accessed internally.
3
HTEN
High Temperature Enable Bit — If set the temperature sense is enabled.
0 The temperature sense is disabled.
1 The temperature sense is enabled.
2
HTDS
High Temperature Detect Status Bit —
0 Temperature TDIE is below level THTID or RPM or Shutdown Mode.
1 Temperature TDIE is above level THTIA and FPM.
1
HTIE
High Temperature Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever HTIF is set.
0
HTIF
High Temperature Interrupt Flag —
0 No change in HTDS bit.
1 HTDS bit has changed.
Note: On entering the reduced power mode the HTIF is not cleared by the VREG.