參數(shù)資料
型號: SC18IS600IBS,151
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: I2C BUS CONTROLLER, PQCC24
封裝: 4 X 4 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT616-3, HVQFN-24
文件頁數(shù): 30/30頁
文件大?。?/td> 164K
代理商: SC18IS600IBS,151
SC18IS600_601_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 28 July 2008
9 of 30
NXP Semiconductors
SC18IS600/601
SPI to I2C-bus interface
6.2.2 I/O pins state register (IOState)
When read, this register returns the actual state of all programmable and
quasi-bidirectional I/O pins. When written, each register bit will be transferred to the
corresponding I/O pin programmed as output.
6.2.3 I2C-bus address register (I2CAdr)
The contents of the register represents the device’s own I2C-bus address. The most
signicant bit corresponds to the rst bit received from the I2C-bus after a START
condition. The least signicant bit is not used, but should be programmed with a ‘0’.
I2CAdr is not needed for device operation, but should be congured so that its address
does not conict with an I2C-bus device address used by the bus master.
6.2.4 I2C-bus clock rates register (I2CClk)
This register determines the I2C-bus clock frequency. Various clock rates are shown in
Table 6 for the SC18IS600. The frequency can be determined using Equation 1:
(1)
Fig 9.
Push-pull output conguration
002aab885
strong
VDD
P
VSS
pin latch data
GPIO pin
glitch rejection
input data
N
Table 5.
IOState - I/O pins state register (address 0x01) bit description
Bit
Symbol
Description
7:6
-
reserved
5
IO5
Set the logic level on the output pins.
Write to this register:
logic 0 = set output pin to zero
logic 1 = set output pin to one
A read from this register returns states of all pins.
4
IO4
3
GPIO3 (SC18IS600 only)
2
GPIO2
1
GPIO1
0
GPIO0
I
2
C-bus clock frequency
7.3728
10
6
×
4
I 2CClk
×
------------------------------- Hz
()
=
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