參數(shù)資料
型號(hào)： SC18IS600IBS,151
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： I2C BUS CONTROLLER, PQCC24
封裝： 4 X 4 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT616-3, HVQFN-24
文件頁(yè)數(shù)： 27/30頁(yè)
文件大?。?/td> 164K
代理商： SC18IS600IBS,151
SC18IS600_601_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 28 July 2008
6 of 30
NXP Semiconductors
SC18IS600/601
SPI to I2C-bus interface
6.
Functional description
The SC18IS600/601 acts as a bridge between a SPI interface and an I2C-bus. It allows a
SPI master device to communicate with I2C-bus slave devices. The SPI interface supports
Mode 3 of the SPI specication and can operate up to 3 Mbit/s (SC18IS601).
6.1 Internal registers
The SC18IS600/601 provides internal registers for monitoring and control. These
registers are shown in Table 3. Register functions are more fully described in the following
paragraphs.
[1]
For SC18IS601, these bits are ‘Don’t care’.
[2]
For SC18IS601 GPIO3 is not used.
6.2 Register descriptions
6.2.1 Programmable IO port conguration register (IOCong)
Pins GPIO0 to GPIO3 may be congured by software to one of four types. These are:
quasi-bidirectional, push-pull, open-drain, and input-only. Two conguration bits per pin,
located in the IOCong register, select the IO type for each pin. Each pin has
Schmitt-triggered input that also has a glitch suppression circuit. IO4 and IO5 are
quasi-bidirectional pins and are not user-congurable. For SC18IS601, GPIO3 is
non-existent.
Table 4 shows the congurations for the programmable I/O pins. IOx.1 and IOx.0
correspond to GPIOx.
Table 3.
Internal registers summary
Register
address
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Default
value
0x00
IOCong
IO3.1[1]
IO2.1
IO2.0
IO1.1
IO1.0
IO0.1
IO0.0
R/W
0x00
0x01
IOState
0
GPIO5
GPIO4
GPIO3[2]
GPIO2
GPIO1
GPIO0
R/W
0x3F
0x02
I2CClock
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
R/W
0x19
0x03
I2CTO
TO6
TO5
TO4
TO3
TO2
TO1
TO0
TE
R/W
0xFE
0x04
I2CStat
1
I2CSTAT3 I2CSTAT2 I2CSTAT1 I2CSTAT0 R
0xF0
0x05
I2CAdr
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
X
R/W
0x00
Table 4.
Pin congurations
IOx.1
IOx.0
Pin conguration
0
quasi-bidirectional output conguration
0
1
input-only conguration
1
0
push-pull output conguration
1
open-drain output conguration
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