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參數(shù)資料
| 型號： | SB83C196NP |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | SQFP-100 |
| 文件頁數(shù)： | 6/33頁 |
| 文件大?。?/td> | 1159K |
| 代理商： | SB83C196NP |
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14
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
ONCE
I
On-circuit Emulation
Holding ONCE high during the rising edge of RESET# places the
device into on-circuit emulation (ONCE) mode. This mode puts all
pins into a high-impedance state, thereby isolating the device from
other components in the system. The value of ONCE is latched
when the RESET# pin goes inactive. While the device is in ONCE
mode, you can debug the system using a clip-on emulator. To exit
ONCE mode, reset the device by pulling the RESET# signal low. To
prevent accidental entry into ONCE mode, connect the ONCE pin to
V
SS.
—
P1.3:0
P1.4
P1.5
P1.6
P1.7
I/O
Port 1
This is a standard, bidirectional port that is multiplexed with individu-
ally selectable special-function signals.
EPA3:0
T1CLK
T1DIR
T2CLK
T2DIR
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
I/O
Port 2
This is a standard, bidirectional port that is multiplexed with individu-
ally selectable special-function signals.
TXD
RXD
EXTINT0
BREQ#
EXTINT1
HOLD#
HLDA#
CLKOUT
P3.5:0
P3.6
P3.7
I/O
Port 3
This is an 8-bit, bidirectional, standard I/O port.
CS5:0#
EXTINT2
EXTINT3
P4.2:0
P4.3
I/O
Port 4
This is a 4-bit, bidirectional, standard I/O port with high-current drive
capability.
PWM2:0
O
Pulse Width Modulator Outputs
These are PWM output pins with high-current drive capability. The
duty cycle and frequency-pulse-widths are programmable.
P4.2:0
RD#
O
Read
Read-signal output to external memory. RD# is asserted only during
external memory reads.
—
READY
I
Ready Input
This active-high input signal is used to lengthen external memory
cycles for slow memory by generating wait states in addition to the
wait states that are generated internally.
When READY is high, CPU operation continues in a normal manner
with wait states inserted as programmed in the chip configuration
registers, Register 0, or the chip-select x bus control register.
READY is ignored for all internal memory accesses.
—
Table 8. Pin Descriptions (Continued)
Name
Type
Description
Multiplexed
with
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