參數(shù)資料
型號(hào)： SB83C196NP
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP100
封裝： SQFP-100
文件頁(yè)數(shù)： 4/33頁(yè)
文件大?。?/td> 1159K
代理商： SB83C196NP
12
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
BHE#
O
Byte High Enable
The chip configuration register 0 (CCR0) determines whether this
pin functions as BHE# or WRH#. CCR0.2=1 selects BHE#;
CCR0.2=0 selects WRH#.
During 16-bit bus cycles, this active-low output signal is asserted for
word reads and writes and high-byte reads and writes to external
memory. BHE# indicates that valid data is being transferred over the
upper half of the system data bus. Use BHE#, in conjunction with
A0, to determine which memory byte is being transferred over the
system bus:
BHE#
A0
Byte(s) Accessed
0
both bytes
0
1
high byte only
1
0
low byte only
WRH#
BREQ#
O
Bus Request
This active-low output signal is asserted during a hold cycle when
the bus controller has a pending external memory cycle.
The device can assert BREQ# at the same time as or after it asserts
HLDA#. Once it is asserted, BREQ# remains asserted until HOLD#
is removed.
You must enable the bus-hold protocol before using this signal.
P2.3
CLKOUT
O
Clock Output
Output of the internal clock generator. The CLKOUT frequency is
the internal operating frequency (F
XTAL1). CLKOUT has a 50% duty
cycle.
P2.7
CS5#:0
O
Chip-select Lines 0–5
The active-low output CSx# is asserted during an external memory
cycle when the address to be accessed is in the range programmed
for chip select x. If the external memory address is outside the
range assigned to the six chip selects, no chip-select output is
asserted and the bus configuration defaults to the CS5# values.
Immediately following reset, CS0# is automatically assigned to the
range FF2000–FF20FFH (F2000–F20FFH if external).
P3.5:0
EA#
I
External Access
This input determines whether memory accesses to special-pur-
pose and program memory partitions (FF2000–FF2FFFH) are
directed to internal or external memory. These accesses are
directed to internal memory if EA# is held high and to external mem-
ory if EA# is held low. For an access to any other memory location,
the value of EA# is irrelevant.
EA# is not latched and can be switched dynamically during normal
operating mode. Be sure to thoroughly consider the issues, such as
different access times for internal and external memory, before
using this dynamic switching capability.
On devices with no internal nonvolatile memory, always connect
EA# to V
SS.
—
Table 8. Pin Descriptions (Continued)
Name
Type
Description
Multiplexed
with
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