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參數(shù)資料
| 型號： | SB83C196NP |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | SQFP-100 |
| 文件頁數(shù)： | 27/33頁 |
| 文件大?。?/td> | 1159K |
| 代理商： | SB83C196NP |
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8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
8XC196NP ERRATA
Change identifiers have been used on embedded products since 1990. The change identifier is the last
character in the FPO number. The FPO number is typically a nine character number located on the second
line of the topside package mark. The following errata listing is applicable to the B–step (denoted by a “B” or
“C” at the end of the topside tracking number):
1.
Any jump, conditional jump, or call instruction located within six bytes of the top of a page, i.e., 0FFFA–
0FFFFH, may cause a jump to the wrong page. To ensure this problem does not occur, place at least six
NOPs at the top of each page.
The following errata listing is applicable to the A–step (denoted by an “A” at the end of the topside tracking
number):
1.
Any jump, conditional jump, or call instruction located within six bytes of the top of a page, i.e., 0FFFA–
0FFFFH, may cause a jump to the wrong page. To ensure this problem does not occur, place at least six
NOPs at the top of each page.
1. The illegal opcode interrupt vector is not taken when an illegal opcode is encountered. A branch to an
unknown location occurs.
2. (1-Mbyte mode only.) If an interrupt is aborted, intentionally or unintentionally, an undesired branch to the
lowest priority interrupt vector (FF2000H) may occur even if the lowest priority interrupt is not enabled.
This may occur if any bit in the INT_MASK, INT_MASK1, INT_PEND, or INT_PEND1 register is cleared
after the corresponding INT_PEND or INT_PEND1 bit is set.
3. (1-Mbyte mode only.) If a standard interrupt occurs at approximately the same time (this time is code
dependent and therefore cannot be stated as an exact number of state times) as a PTS serviced
interrupt, the PTS interrupt may be processed as a standard interrupt. The standard interrupt service
routine for a PTS serviced interrupt (End-of-PTS) is typically used to modify the PTS control block and re-
enable the PTS by setting the corresponding bit in the PTSSEL register. When this anomaly occurs, the
End-of-PTS service routine will execute regardless of the value in PTSCOUNT. As a result, an undeter-
mined number of PTS cycles will not occur. This applies to all PTS interrupts.
DATA SHEET REVISION HISTORY
This data sheet is valid for devices with a “B” at the end of the topside tracking number. Data sheets are
changed as new device information becomes available. Verify with your local Intel sales office that you have
the latest version before finalizing a design or ordering devices.
The following are important changes to the 272459-006 datasheet:
1.
To address the fact that many of the package prefix variables have changed, all package prefix variables
in the document are now indicated with an "x".
The following are important changes to the 272459-005 datasheet:
1.
Revised Tables 8 through 15 and Figures 5, 6, 7, and 13 to reflect new or changed information.
2.
Added Table 3 and Figure 9.
3.
The input frequency on XTAL1, formerly called F
OSC, is now denoted by FXTAL1.
4.
The AC characteristics tables have been divided into the following: the timing specifications met by the
device, and the timing specifications that must be met by the external memory system.
5.
Maximum IOL and IOH specifications added to the DC characteristics tables.
6.
AC timings T
AVWL and TAVRL added to the AC characteristics–multiplexed bus mode tables.
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