參數(shù)資料
型號: SB83C196NP
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP100
封裝: SQFP-100
文件頁數(shù): 3/33頁
文件大?。?/td> 1159K
代理商: SB83C196NP
11
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
PIN DESCRIPTIONS
Table 8. Pin Descriptions
Name
Type
Description
Multiplexed
with
A15:0
I/O
System Address Bus
These address lines provide address bits 0–15 during the entire
external memory cycle during both multiplexed and demultiplexed
bus modes.
A19:16
I/O
Address Lines 16–19
These address lines provide address bits 16–19 during the entire
external memory cycle, supporting extended addressing of the 1-
Mbyte address space.
Internally, there are 24 address bits; however, only 20 address lines
(A19:0) are bonded out. The external address space is 1 Mbyte
(00000–FFFFFH) and the internal address space is 16 Mbytes
(000000–FFFFFFH). The 8XC196NP resets to internal address
FF2080H (FF2080H in internal ROM or F2080H in external mem-
ory).
EPORT.3:0
AD15:0
I/O
Address/Data Lines
The function of these pins depends on the bus size and mode.
16-bit Multiplexed Bus Mode:
AD15:0 drive address bits 0–15 during the first half of the bus cycle
and drive or receive data during the second half of the bus cycle.
8-bit Multiplexed Bus Mode:
AD15:8 drive address bits 8–15 during the entire bus cycle. AD7:0
drive address bits 0–7 during the first half of the bus cycle and drive
or receive data during the second half of the bus cycle.
16-bit Demultiplexed Mode:
AD15:0 drive or receive data during the entire bus cycle.
8-bit Demultiplexed Mode:
AD7:0 drive or receive data during the entire bus cycle. AD15:8
drive the data that is currently on the high byte of the internal bus.
ALE
O
Address Latch Enable
This active-high output signal is asserted only during external mem-
ory cycles. ALE signals the start of an external bus cycle and indi-
cates that valid address information is available on the system
address/data bus (A19:16 and AD15:0 for a multiplexed bus; A19:0
for a demultiplexed bus). ALE differs from ADV# in that it does not
remain active during the entire bus cycle.
An external latch can use this signal to demultiplex the address bits
0–15 from the address/data bus in multiplexed mode.
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