參數(shù)資料
型號(hào)： SB83C196NP
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP100
封裝： SQFP-100
文件頁(yè)數(shù)： 5/33頁(yè)
文件大?。?/td> 1159K
代理商： SB83C196NP
13
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
EPA3:0
I/O
Event Processor Array (EPA) Input/Output pins
These are the high-speed input/output pins for the EPA cap-
ture/compare channels. For high-speed PWM applications, the out-
puts of two EPA channels (either EPA0 and EPA1 or EPA2 and
EPA3) can be remapped to produce a PWM waveform on a shared
output pin.
P1.3:0
EPORT.3:0
I/O
Extended Addressing Port
This is a 4-bit, bidirectional, memory-mapped I/O port. The pins are
shared with the extended address bus A19:16.
A19:16
EXTINT0
EXTINT1
EXTINT2
EXTINT3
I
External Interrupts
In normal operating mode, a rising edge on EXTINTx sets the
EXTINTx interrupt pending bit. EXTINTx is sampled during phase 2
(CLKOUT high). The minimum high time is one state time.
In powerdown mode, asserting the EXTINTx signal for at least 1
state time causes the device to resume normal operation. The inter-
rupt need not be enabled, but the pin must be configured as a spe-
cial-function input. If the EXTINTx interrupt is enabled, the CPU
executes the interrupt service routine. Otherwise, the CPU executes
the instruction that immediately follows the command that invoked
the power-saving mode.
In idle mode, asserting any enabled interrupt causes the device to
resume normal operation.
P2.2
P2.4
P3.6
P3.7
HLDA#
O
Bus Hold Acknowledge
This active-low output indicates that the CPU has released the bus
as the result of an external device asserting HOLD#.
P2.6
HOLD#
I
Bus Hold Request
An external device uses this active-low input signal to request con-
trol of the bus. This pin functions as HOLD# only if the pin is config-
ured for its special function and the bus-hold protocol is enabled.
Setting bit 7 of the window selection register enables the bus-hold
protocol.
P2.5
INST
O
Instruction Fetch
This active-high output signal is valid only during external memory
bus cycles. When high, INST indicates that an instruction is being
fetched from external memory. The signal remains high during the
entire bus cycle of an external instruction fetch. INST is low for data
accesses, including interrupt vector fetches and chip configuration
byte reads. INST is low during internal memory fetches.
—
NMI
I
Nonmaskable Interrupt
In normal operating mode, a rising edge on NMI generates a non-
maskable interrupt. NMI has the highest priority of all prioritized
interrupts. Assert NMI for greater than one state time to guarantee
that it is recognized.
—
Table 8. Pin Descriptions (Continued)
Name
Type
Description
Multiplexed
with
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