
261
8155C–AVR–02/11
ATmega32A
25.8.8
EEPROM Write Prevents Writing to SPMCR
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCR Register.
25.8.9
Reading the Fuse and Lock Bits from Software
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with $0001 and set the BLBSET and SPMEN bits in SPMCR. When an LPM instruction
is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCR, the
value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN bits
will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed
within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLB-
SET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.
The algorithm for reading the Fuse Low bits is similar to the one described above for reading the
Lock bits. To read the Fuse Low bits, load the Z-pointer with $0000 and set the BLBSET and
SPMEN bits in SPMCR. When an LPM instruction is executed within three cycles after the BLB-
SET and SPMEN bits are set in the SPMCR, the value of the Fuse Low bits (FLB) will be loaded
in the destination register as shown below. Refer to Table 26-4 on page 268 for a detailed
description and mapping of the Fuse Low bits.
Similarly, when reading the Fuse High bits, load $0003 in the Z-pointer. When an LPM instruc-
tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR,
the value of the Fuse High bits (FHB) will be loaded in the destination register as shown below.
Refer to Table 26-3 on page 267 for detailed description and mapping of the Fuse High bits.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
25.8.10
Preventing Flash Corruption
During periods of low V
CC, the Flash program can be corrupted because the supply voltage is too
low for the CPU and the Flash to operate properly. These issues are the same as for board level
systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
Bit
7
6
543210
Rd
–
BLB12
BLB11
BLB02
BLB01
LB2
LB1
Bit
7
65
4
3210
Rd
FLB7
FLB6
FLB5
FLB4
FLB3
FLB2
FLB1
FLB0
Bit
7
65
4
3210
Rd
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0