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參數(shù)資料
| 型號： | SAA7390GP |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | High performance Compact Disc-Recordable CD-R controller |
| 中文描述： | 高性能式光盤CD - R光盤控制器 |
| 文件頁數(shù)： | 57/76頁 |
| 文件大小： | 366K |
| 代理商： | SAA7390GP |
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1996 Jul 02
57
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
SAA7390
15.6
SPI interface timing
The control communication between the CD-R engine and
the interface module is based on data blocks that are
swapped in the same cycle.
The control communication channel is byte and message
synchronous. Byte synchronization is realized with an
acknowledge after each byte that is transferred. Message
synchronization is ensured through resetting the serial
shift register after each communication synchronization
pulse. This is to detect the start of the next data block even
if a time-out or bit-slip occurs.
This control interface is used for the exchange of:
Sub-code data
Commands with parameters
Status information.
The control interface channel is implemented as a
bidirectional, synchronous, high-speed serial link, having
the following advantages:
The Q sub-code and header data can be coupled
(synchronized)
The user part has real time access of the Q sub-code
information
The user part has full control over the CD-R engines
mode of operation, for example synchronous stop while
recording
High speed data transfers are possible; up to 2 Mbits/s
for the microcontroller in slave mode.
Table 78
SPI timing parameters
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
T
cy
t
CH
t
CL
t
su
t
h
t
d
serial clock cycle time
serial clock HIGH time
Serial clock LOW time
serial input data set-up time to COM_CLK
serial input data hold time from COM_CLK
serial output delay after COM_CLK
500
210
210
80
80
0
150
ns
ns
ns
ns
ns
ns
Fig.21 Serial communication timing and synchronization.
handbook, full pagewidth
MGE523
COMM_SYNC
engine data available
COM_ACK
user data available
COM_CLK
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