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參數(shù)資料
| 型號(hào)： | SAA7390GP |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | High performance Compact Disc-Recordable CD-R controller |
| 中文描述： | 高性能式光盤CD - R光盤控制器 |
| 文件頁數(shù)： | 36/76頁 |
| 文件大小： | 366K |
| 代理商： | SAA7390GP |
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1996 Jul 02
36
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
SAA7390
Table 48
Buffer manager front-end control: 0xF0E1
Table 49
BMFECTL field descriptions
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
BMFECTL
R/W
STOP
FEWBLK
HW_BLK
TDB_EN
FIELD
LOGIC
DESCRIPTION
TDB_EN
Track Descriptor Block (TDB) enable; default LOW. When set, this causes the buffer
manager to continuously output the frame addressed by TBDL/TDBH for as many frames as
programmed into TDB_CNT. TDB_CNT can be read and re-initialized while the TDB is being
sent to the CDB2 to extend the count beyond 256.
Host write block. If set HIGH, this bit will prevent a write to the host start frame number
register (HOSTSFRM) for immediately changing the host frame counter (HOSTCFRM).
The new value will be loaded at the next roll-over; a roll-over occurs when the host frame
counter reaches the maximum frame number (LASTHOST) and is reloaded with the host
start frame number.
Front-end write block. If set HIGH, this bit will prevent a write to the front-end start frame
number register (FEFRM#) from immediately changing the front-end counter. The new value
will be loaded at the next roll-over; a roll-over occurs when the front-end frame counter
reaches the maximum frame number (LASTFRM) and is reloaded with the front-end start
frame number (FEFRM#).
Automatic START control registers are selected.
Automatic STOP control registers are selected.
HW_BLK
FEWBLK
STOP
0
1
11.2
Microcontroller to buffer manager interface
The microcontroller interface allows the microcontroller to
read or write any register or the frame store memory.
Frame and offset registers are used to update the counters
after the most significant byte has been loaded. Frame
store memory is addressed using a frame number register
controller by the microcontroller. Logic is provided to allow
the frame number of the last complete frame received
(LSTCMPFM) from the front-end to be read by the
microcontroller for the purpose of setting the
microcontroller frame address.
Memory beyond the last frame number is available to the
microcontroller using the microcontroller bottom 32 kbytes
located at 0x0000 to 0x7FFF. The 4 kbytes segment at
0x8000 to 0x8FFF is used to address the current frame
memory. Also, the next frame may be accessed at
0x9000 to 0x9FFF, and the current frame plus 2 may be
accessed at 0xA000 to 0xAFFF.
A page register is provided to allow the microcontroller to
address the complete memory range in 32 kbytes pages.
All microcontroller accesses to memory are single byte
read or write cycles.
All microcontroller accesses to memory will generate a
wait state. If no other accesses to memory are in progress
then a minimum wait state cycle will be generated. If,
however, other cycles are in progress then the
microcontroller is forced to wait until the lower priority
access cycles finish and any high priority access cycles
are completed. The worst case wait is four complete
access cycles; a total of 20 clock cycles.
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