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1996 Jul 02
28
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
SAA7390
Table 28
UARTCTL field descriptions
Table 29
SAA7390 to basic engine communication port: 0xF0C4; note 1
Note
1.
Register 0xF0C4 provides a serial communication path to the basic engine processor. Writing a byte to this register
automatically clocks the bits to the other processor. As the bits shift out, a byte from the basic engine processor is
shifted in. The bit rate is 2 Mbits/s. Handshake with the basic engine is accomplished with COM_ACK.
9.3
Track Descriptor Block (TDB) generation
A special mode has been included to support automatic TDB generation. Basically, the host writes one frame of the TDB
into the buffer and programs its address into TDB. Then the number of frames to repeat this pattern is programmed in
TDB_CNT. Once this has been carried out, TDB_EN in FEBMCTL is set. When the frame counter equals the contents
of TDB, the TDB frame will be repeated as many times as programmed by TDB_CNT. If more than 256 frames are
required for the TDB, TDB_CNT can be read back and re-programmed with a new value. This action must be carried out
as soon as possible after an end-of-frame to prevent the count value from being corrupted.
Table 30
Track descriptor block count: 0xF08F; note 1
Note
1.
The loadable down counter holds the TDB frame count. TDB_CNT can be read while a TDB is being sent to the
CDB2 and may be re-written with a new value to extend the length of the TDB beyond 256 frames; which should be
carried out as soon as possible after an end-of-frame.
FIELD
DESCRIPTION
CSD_SEL
CSU_SEL
SSD_SEL
SSU_SEL
CSD_REP
CSU_REP
SSD_REP
SSU_REP
elects COM_SYNC falling edge when set
selects COM_SYNC rising edge when set
selects SYS_SYNC falling edge when set
selects SYS_SYNC rising edge when set
reports COM_SYNC falling edge when set
reports COM_SYNC rising edge when set
reports SYS_SYNC falling edge when set
reports SYS_SYNC rising edge when set
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
SERCOM
R/W
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
TDB_CNT
R/W
TDB count 7 to TDB count 0