參數(shù)資料
型號(hào): SAA7390GP
廠商: NXP Semiconductors N.V.
英文描述: High performance Compact Disc-Recordable CD-R controller
中文描述: 高性能式光盤CD - R光盤控制器
文件頁(yè)數(shù): 24/76頁(yè)
文件大小: 366K
代理商: SAA7390GP
1996 Jul 02
24
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
SAA7390
9
FRONT PANEL AND MISCELLANEOUS CONTROL SIGNALS
This Chapter describes the various SAA7390 control signals; front panel and basic engine signals, jumper settings and
use of the general purpose signals.
Table 14
Start clock doubler: 0xF091
A write of any value to this address will engage the clock doubler. The state of the doubler may be obtained by reading
C_34_16 in BRGSEL (see Table 26). If this bit is set then the clock doubler is engaged. On power-on, the clock doubler
is disabled. Once the clock doubler is engaged, it can only be reset by one of the reset sources; a power-on reset, an
SCSI reset or a reset from the watch-dog timer. The clock doubler must not be engaged when a 34.8688 MHz clock is
connected to OSCIN (pin 120).
Table 15
General logic control register: 0xF0B9; note 1
Note
1.
Register 0xF0B9 controls the audio mixing, the LED and the PWM control.
Table 16
WTGCTL field descriptions
Table 17
Drive switches register: 0xF0BA; note 1
Note
1.
Register 0xF0BA is used for sensing the drive switches (note that the meaning of the switches is application specific).
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
CLKSEL
W
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
WTGCTL
W
PWMSEL
LED
LA_MUTE RA_MUTE CHANNEL1 CHANNEL0
FIELD
LOGIC
DESCRIPTION
CHANNELS
00
01
10
11
0
1
mute
right data sent to both channels
left data sent to both channels
stereo
right channel digital mute
left channel digital mute
active LOW control for the light emitting diode
CD decoder output (default); e.g. CD-60 MOTO1 output
PWM output
RA_MUTE
LA_MUTE
LED
PWMSEL
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
RDSW
R
HFD
VOLUP
VOLDN
EJECT
TRAYSW
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