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參數(shù)資料
| 型號： | SAA7390GP |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | High performance Compact Disc-Recordable CD-R controller |
| 中文描述： | 高性能式光盤CD - R光盤控制器 |
| 文件頁數(shù)： | 13/76頁 |
| 文件大?。?/td> | 366K |
| 代理商： | SAA7390GP |
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1996 Jul 02
13
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
SAA7390
7.5
Buffer manager
The buffer manager provides the arbitration for the
different processes that wish to access the DRAM buffer.
These processes include the front-end, microcontroller
requests, CDB2 accesses, ECC accesses, host interface
requests and DRAM refreshing.
To manage a DRAM interface with up to four devices
requesting access to the DRAM, the following priority
scheme is used. The DRAM control logic will start an
access on the next rising edge of the clock after a request
is received. If two or more requests are pending then the
priority is:
1.
Front-end (highest priority)
2.
A refresh cycle (required every 15.6
μ
s) granted
priority for one access
3.
Microcontroller requests
4.
Host interface requests
5.
ECC requests (lowest priority).
A burst access by ECC or host interface will only be
interrupted by a higher priority access request.
In addition to the priority logic, logic is required for the
front-end sources of data. The priority is; CDB2 requests
(highest) frame data, flag data, sub-code data, Q-channel
data and finally status byte. All front-end sources are
granted priority over the host interface logic, ECC, refresh
and data will be written into the frame store during the next
cycle. However, the microcontroller has priority over the
lower three front-end sources and will be granted an
access after front-end frame data or flag data is written to
memory.
The required timing (see Figs 4 to 11) operate with the
industry standard 70 ns DRAMs. The interface is designed
to operate with 256 kbytes, 1 Mbyte, and 4 Mbytes of
DRAM. A single byte access cycles requires five clock
cycles of 29.5 ns each, totalling 147.5 ns.
Fig.4 Byte mode single access read cycle.
handbook, full pagewidth
MGE392
DOE
ADDRESS
ROW
COL
DATA
CAS
RAS
CLOCK
latch data
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