參數(shù)資料
型號(hào): SAA7378GP
廠商: NXP Semiconductors N.V.
英文描述: Single Chip Digital Servo Processor and Compact Disc Decoder
中文描述: 單片機(jī)數(shù)字伺服處理器和光盤解碼器
文件頁數(shù): 40/45頁
文件大?。?/td> 224K
代理商: SAA7378GP
Philips Semiconductors
Preliminary specification: Version 1.0
May 1995
40
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
10.3
V
DD
= 3.4 to 5.5 V; V
SS
= 0; T
amb
= 5 to 70
°
C; unless otherwise stated.
Operating Characteristics (
μ
P
Interface Timing)
Notes:
1)
Negative set-up time means that the data may change after clock transition.
SYMBOL
μ
P interface timing (writing to registers 0 to F; reading Q-channel subcode and decoder status) see
Figure 29 and Figure 30.
Inputs SCL and RAB
t
L
input LOW time
t
H
input HIGH time
t
R
rise time
t
F
fall time
Read mode
(CL = 20pF)
t
DRD
delay time RAB to SDA valid
t
DD
propagation delay SCL to SDA
t
DRZ
delay time RAB to SDA hi-impedance
Write mode
(CL = 20pF)
t
SD
setup time SDA to SCL
note 1
t
HD
hold time SCL to SDA
t
SCR
setup time SCL to RAB
t
DWZ
delay time SDA hi-impedance to RAB
μ
P interface timing (servo commands) see Figure 31 and Figure 32.
Inputs SCL and SILD
t
L
Input LOW time
t
H
Input HIGH time
t
R
rise time
t
F
fall time
Read mode
(CL = 20pF)
t
DLD
delay time SILD to SDA valid
t
DD
propogation delay SCL to SDA
t
DLZ
delay time SILD to SDA hi-impedance
Write mode
(CL = 20pF)
t
SD
set up time SDA to SCL
t
HD
hold time SCL to SDA
t
SCL
aet up time SCL to SILD
t
HCL
hold time SILD to SCL
t
PLP
delay between two SILD pulses
t
DWZ
delay time SDA hi-impedance to SILD
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
500
500
-
-
-
-
-
-
-
-
480
480
ns
ns
ns
ns
-
700
-
-
-
-
50
980
50
ns
ns
ns
-700
-
260
0
-
-
-
-
-
980
-
-
ns
ns
ns
ns
710
710
-
-
-
-
-
-
-
-
240
240
ns
ns
ns
ns
-
-
-
-
-
-
25
950
50
ns
ns
ns
0
950
480
120
65
0
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
μ
s
ns
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