參數(shù)資料
型號(hào): SAA7378GP
廠商: NXP Semiconductors N.V.
英文描述: Single Chip Digital Servo Processor and Compact Disc Decoder
中文描述: 單片機(jī)數(shù)字伺服處理器和光盤解碼器
文件頁數(shù): 12/45頁
文件大?。?/td> 224K
代理商: SAA7378GP
Philips Semiconductors
Preliminary specification: Version 1.0
May 1995
12
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
7.5
Subcode Data Processing
7.5.1
The 96-bit Q-channel word is accumulated in an internal buffer. The last 16 bits are used internally to perform a Cyclic
Redundancy Check (CRC). If the data is good, the SUBQREADY-Isignal will go low. SUBQREADY-I can be read via the
SDA or STATUS pins, selected via register 2. Good Q-channel data may be read from SDA.
Q-Channel Processing
7.5.2
Data of subcode channels, Q-W, is available in the EBU output (DOBM).
Subcode Channels Q-W
7.6
The SAA7378 has a
±
8 frame FIFO. The error corrector is a t = 2, e = 4 type, with error corrections on both C1 (32 symbol)
and C2 (28 symbol) frames. Four symbols are used from each frame as parity symbols. This error corrector can correct up
to two errors on the C1 level and up to four errors on the C2 level.
The error corrector also contains a flag processor. Flags are assigned to symbols when the error corrector cannot ascertain
if the symbols are definitely good. C1 generates output flags which are read after (de-interleaving) by C2, to help in the
generation of C2 output flags.
The C2 output flags are used by the interpolator for concealment of uncorrectable errors. They are also output via the EBU
signal (DOBM).
FIFO and Error Corrector
7.6.1
The flags output pin CFLG (open-drain) shows the status of the error corrector and interpolator and is updated every frame
7.35kHz. In the SAA7378 chip a 1-bit flag is present on the CFLG pin as shown in Figure 6.This signal shows the status of
the error corrector and interpolator.
Flags Output (CFLG)
F1
F2
F3
F4
F5
F6
F7
F1
11.3
μ
s
33.9
μ
s
F8
F8
33.9
μ
s
Figure 6 Flag Output Timing Diagram
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