
1995 Oct 18
65
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
21 I
2
C-BUS START SET-UP
The values shown in Table 66 are optimized for the EBU colour bar (100% white and 75% chrominance amplitude)
signal. The decoder output signal level fulfils the CCIR 601 specification. The input of 100% colour bar level is possible,
but the signal (white) peak function reduces the digital luminance output. With a different set-up it is possible to proceed
100% colour bar signal without luminance colour bar reduction. The method is to modify the AD input range for this input
level by reducing the gain reference value (SBOT > 06h) and adjusting the digital Y output level with contrast and
brightness control.
Table 66
I
2
C-bus start set-up
SU
NAME
FUNCTION
BINARY
HEX
7
0
0
0
1
1
1
6
1
0
0
1
0
1
5
0
1
0
1
1
1
4
0
1
0
0
1
1
3
1
1
1
1
1
0
2
1
1
1
1
1
0
1
0
0
0
1
0
0
0
0
0
1
1
1
0
start
4C
3C
0D
EF
BD
F0
00
01
02
03
04
05
IDEL7 to IDEL0
HSYB7 to HSYB0
HSYS7 to HSYS0
HCLB7 to HCLB0
HCLS7 to HCLS0
HPHI7 to HPHI0
BYPS, PREF,
BPSS1 to BPSS0,
CORI1 to CORI0,
APER1 to APER0
HUEC7 to HUEC0
CKTQ4 to CKTQ0, XXX
CKTS4 to CKTS0, XXX
PLSE7 to PLSE0
SESE7 to SESE0
COLO, LFIS1 to LFIS0,
XXXXX
VTRC, XXX, RTSE, HRMV,
SSTB, SECS
HPLL, XX, OEHV, OEYC,
CHRS, X, GPSW
AUFD, FSEL, SXCR, SCEN,
X, YDEL2 to YDEL0
XXXXX, HRFS,
VNOI1 to VNOI0
CHCV7 to CHCV0 PAL
CHCV7 to CHCV0 NTSC
SATN7 to SATN0
CONT7 to CONT0
HS6B7 to HS6B70
HS6S7 to HS6S0
HC6B7 to HC6B0
HC6S7 to HC6S0
HP6I7 to HP6I0
BRIGI7 to BRIG0
increment delay
horizontal sync (HSY) begin 50 Hz
horizontal sync (HSY) stop 50 Hz
horizontal clamp (HCL) begin 50 Hz
horizontal clamp (HCL) stop 50 Hz
horizontal sync after PHI1 50 Hz
06
luminance control
0
0
0
0
0
0
0
0
00
07
08
09
0A
0B
hue control
colour killer threshold PAL
colour killer threshold SECAM
PAL switch sensitivity
SECAM switch sensitivity
gain control chrominance
0
1
1
0
0
0
1
1
1
1
0
1
1
1
1
0
1
1
0
0
0
1
1
0
0
0
X
X
0
0
0
X
X
0
0
0
X
X
0
0
00
F8
F8
60
5B
0C
0
0
0
X
X
X
X
X
00
0D
standard/mode control
0
X
X
X
0
1
1
0
06
0E
I/O and clock control
0
X
X
1
1
0
X
0
18
0F
control #1
1
0
0
1
X
0
0
0
90
10
control #2
X
X
X
X
X
0
0
0
00
11
chrominance gain reference
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
0
1
1
1
0
0
1
0
0
0
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
1
1
0
0
0
1
1
1
0
1
0
1
0
1
0
0
1
0
0
0
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
1
0
0
1
59
2C
40
46
42
1A
FF
DA
F0
8B
12
13
14
15
16
17
18
19
chrominance saturation
luminance contrast
horizontal sync (HSY) begin 60 Hz
horizontal sync (HSY) stop 60 Hz
horizontal clamp (HCL) begin 60 Hz
horizontal clamp (HCL) stop 60 Hz
horizontal sync after PHI1 60 Hz
luminance brightness