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參數(shù)資料
| 型號： | SAA7110 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Digital Multistandard Colour Decoder(數(shù)字多標準彩色譯碼器) |
| 中文描述： | COLOR SIGNAL DECODER, PQCC68 |
| 封裝： | PLASTIC, MO-047AC, SOT-188-2, LCC-68 |
| 文件頁數(shù)： | 7/76頁 |
| 文件大?。?/td> | 416K |
| 代理商： | SAA7110 |
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1995 Oct 18
7
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
RESET
32
Reset active LOW input/output (CGCE = 1, output; CGCE = 0, input); sets the device into a
defined state. All data outputs are in high impedance state. The I
2
C-bus is reset (waiting for
START condition). Using the external CGC, the LOW period must be maintained for at least
30 LLC clock cycles.
CGC Enable active HIGH input (CGCE = 1, on-chip CGC active; CGCE = 0, external CGC
mode, use SAA7197).
supply voltage (+5 V)
ground
Horizontal Clamping input/output pulse (programmable via I
2
C-bus bit PULIO: PULIO = 1,
output; PULIO = 0, input). This signal is used to indicate the black level clamping period for
the analog input interface. The beginning and end of its HIGH period (only in the output mode)
can be programmed via the I
2
C-bus registers 03H, 04H in 50 Hz mode and registers 16H,
17H in 60 Hz mode, active HIGH.
Horizontal Synchronization input/output indicator (programmable via I
2
C-bus bit PULIO:
PULIO = 1, output; PULIO = 0, input). This signal is fed to the analog interface. The beginning
and end of its HIGH period (only in the output mode) can be programmed via the I
2
C-bus
registers 01H, 02H in 50 Hz mode and registers 14H, 15H in 60 Hz mode, active HIGH.
Horizontal Synchronization output (programmable; the HIGH period is 128 LLC clock cycles).
The position of the positive slope is programmable in 8 LLC increments over a complete line
(64
μ
s) via the I
2
C-bus register 05H in 50 Hz mode or register 18H in 60 Hz mode.
PAL Identifier Not output; marks for demodulated PAL signals the inverted line (PLIN = LOW)
and a non-inverted line (PLIN = HIGH) and for demodulated SECAM the DR line
(PLIN = LOW) and the DB line (PLIN = HIGH). Select PLIN function via I
2
C-bus bit RTSE = 0.
(H-PLL locked output; a HIGH state indicates that the internal PLL has locked. Select HL
function via I
2
C-bus bit RTSE = 1).
ODD/EVEN field identification output; a HIGH state indicates the odd field. Select ODD
function via I
2
C-bus bit RTSE = 0.
(Vertical Locked output; a HIGH state indicates that the internal Vertical Noise Limiter (VNL)
is in a locked state. Select VL function via I
2
C-bus bit RTSE = 1).
Vertical Synchronization input/output (programmable via I
2
C-bus bit OEHV: OEHV = 1,
output; OEHV = 0, input). This signal indicates the vertical synchronization with respect to the
YUV output. The high period of this signal is approximately six lines if the VNL function is
active. The positive slope contains the phase information for a deflection controller, for
example the TDA9150. In input mode this signal is used to synchronize the vertical gain and
clamp blanking stage, active HIGH.
Horizontal Reference output; this signal is used to indicate data on the digital YUV-bus. The
positive slope marks the beginning of a new active line. The HIGH period of HREF is either
768 Y samples or 640 Y samples long depending on the detected field frequency
(50/60 Hz mode). HREF is used to synchronize data multiplexer/demultiplexers. HREF is also
present during the vertical blanking interval.
ground
supply voltage (+5 V)
CGCE
33
V
DD
V
SS
HCL
34
35
36
HSY
37
HS
38
PLIN (HL)
39
ODD (VL)
40
VS
41
HREF
42
V
SS
V
DD
43
44
SYMBOL
PIN
DESCRIPTION
相關PDF資料 |
PDF描述 |
|---|---|
| SAA7111 | Video Input Processor VIP |
| SAA7120H | Digital video encoder |
| SAA7152 | Digital Video Comb Filter DCF |
| SAA7184 | Digital Video Encoders DENC2-M6 |
| SAA7187 | Digital video encoder (DENC2-SQ)(數(shù)字視頻編碼器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7110/7110A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:One Chip Frontend 1 (OCF1) Product Specification |
| SAA7110A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:One Chip Front-end 1 OCF1 |
| SAA7110AWP/00 | 制造商:NXP Semiconductors 功能描述: |
| SAA7111 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Video Input Processor VIP |
| SAA7111A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Video Input Processor EVIP |
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