參數(shù)資料
型號: SAA7110
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號轉(zhuǎn)換
英文描述: Digital Multistandard Colour Decoder(數(shù)字多標(biāo)準(zhǔn)彩色譯碼器)
中文描述: COLOR SIGNAL DECODER, PQCC68
封裝: PLASTIC, MO-047AC, SOT-188-2, LCC-68
文件頁數(shù): 50/76頁
文件大?。?/td> 416K
代理商: SAA7110
1995 Oct 18
50
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
16.4.13 S
UBADDRESS
2C (
DATA BYTE
103 to 096)
Table 53
Mixer control #2
16.4.14 S
UBADDRESS
2D (
DATA BYTE
111 to 104)
Table 54
Integration value gain (IVAL)
16.4.15 S
UBADDRESS
2E (
DATA BYTE
119 to 112)
Table 55
Blanking pulse VBLK-set (VBPS)
Notes
1.
2.
Maximum for 60 Hz.
Maximum for 50 Hz.
FUNCTION
CONTROL BITS
Two’s complement channel 2 (TWO2); data bit D0
Unipolar
TWO2 = 0
TWO2 = 1
Two’s complement (normal mode)
Two’s complement channel 3 (TWO3); data bit D1
Unipolar
TWO3 = 0
TWO3 = 1
Two’s complement (normal mode)
Clamping level select channel 2 (CLS2); data bit D4
CLL21 active
CLL22 active
CLS2 = 0
CLS2 = 1
Clamping level select channel 3 (CLS3); data bit D5
CLL31 active
CLL32 active
CLS3 = 0
CLS3 = 1
Clamping level select channel 4 (CLS4); data bit D7
CLL2n active
CLL3n active
CLS4 = 0
CLS4 = 1
DECIMAL INTEGRATION VALUE GAIN
CONTROL BITS
IVAL7
IVAL6
IVAL5
IVAL4
IVAL3
IVAL2
IVAL1
IVAL0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
255
DECIMAL
MULTIPLIER
SET LINE NUMBER
(step size = 2)
CONTROL BITS
VBPS7 VBPS6 VBPS5 VBPS4 VBPS3 VBPS2 VBPS1 VBPS0
0
0 after rising edge of VS
262 after rising edge of VS
312 after rising edge of VS
0
1
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
131
(1)
156
(2)
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