參數(shù)資料
型號(hào): SAA7110
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: Digital Multistandard Colour Decoder(數(shù)字多標(biāo)準(zhǔn)彩色譯碼器)
中文描述: COLOR SIGNAL DECODER, PQCC68
封裝: PLASTIC, MO-047AC, SOT-188-2, LCC-68
文件頁數(shù): 34/76頁
文件大?。?/td> 416K
代理商: SAA7110
1995 Oct 18
34
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
Table 10
Explanation of bits shown in Table 9
16.3
I
2
C-bus detail
The I
2
C-bus receiver slave address is 9CH/9EH.
DMSD-SQP slave receiver (SU 00H to 19H).
16.3.1
S
UBADDRESS
00 (
DATA BYTE
007 to 000)
Table 11
Increment delay IDEL
Notes
1.
2.
A sign bit, designated A08 and internally set to HIGH, indicates values are always negative.
The horizontal PLL does not operate in this condition. The system clock frequency is set to a value fixed by the last
update and is within
±
7.1% of the nominal frequency.
BIT
DESCRIPTION
STTC
HLCK
FIDT
GLIM
XXX
WIPA
ALTD
CODE
Status bit for horizontal time constant: LOW = TV time constant; HIGH = VCR time constant.
Status bit for locked horizontal frequency: LOW = locked; HIGH = unlocked.
Identification bit for detected field frequency: LOW = 50 Hz; HIGH = 60 Hz.
Gain value for active luminance is limited (maximum or minimum), active HIGH.
reserved
White peak loop is activated, active HIGH.
Status HIGH: line alternating colour burst has been detected (PAL or SECAM).
Status HIGH: any colour signal has been detected.
DECIMAL
MULTIPLIER
DELAY TIME
(STEP SIZE = 4/LLC)
CONTROL BITS
(1)
IDEL7
IDEL6
IDEL5
IDEL4
IDEL3
IDEL2
IDEL1
IDEL0
1
4
1
0
1
0
1
1
1
1
1
1
1
1
1
0
1
1
195
780
max. value for 60 Hz
944
max. value for 50 Hz
1024
outside central counter
(2)
0
0
0
1
0
1
0
0
236
0
0
0
0
0
0
0
0
256
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