參數(shù)資料
型號: SAA7110
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號轉(zhuǎn)換
英文描述: Digital Multistandard Colour Decoder(數(shù)字多標(biāo)準(zhǔn)彩色譯碼器)
中文描述: COLOR SIGNAL DECODER, PQCC68
封裝: PLASTIC, MO-047AC, SOT-188-2, LCC-68
文件頁數(shù): 40/76頁
文件大?。?/td> 416K
代理商: SAA7110
1995 Oct 18
40
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
16.3.15 S
UBADDRESS
0E (
DATA BYTE
119 to 112)
Table 25
I/O and clock control
16.3.16 S
UBADDRESS
0F (
DATA BYTE
127 to 120)
Table 26
Control number 1
FUNCTION
CONTROL BITS
General purpose switch (GPSW); data bit D0
Switches directly pin 64 GPSW (application dependent);
VBLKA = 0
GPSW = 0
GPSW = 1
Select chrominance input (CHRS); data bit D2
Controlled by BYPS (subaddress 06) normal position
Digital chrominance input switched to
second input channel (see Fig.20)
CHRS = 0
CHRS = 1
Output enable YUV-data (OEYC); data bit D3
YUV bus high impedance/input
Output YUV-bus active
OEYC = 0
OEYC = 1
Output enable horizontal/vertical synchronization (OEHV); data bit D4
HS, HREF and VS high impedance/inputs
Output HS, HREF and VS active
OEHV = 0
OEHV = 1
Horizontal PLL clock (HPLL); data bit D7
PLL closed
HPLL = 0
HPLL = 1
PLL open, horizontal frequency fixed
FUNCTION
CONTROL BITS
Luminance delay compensation; steps in 2/LLC (YDEL); data bits D2, D1 and D0
0 steps
3 steps
4 steps
YDEL2 = 0; YDEL1 = 0; YDEL0 = 0
YDEL2 = 0; YDEL1 = 1; YDEL0 = 1
YDEL2 = 1; YDEL1 = 0 YDEL1 = 0
Enable or disable of sync and clamp pulses; HSY and HCL (SCEN); data bit D4
Disable sync and clamp (set to HIGH)
Enable sync and clamp
SCEN = 0
SCEN = 1
SECAM cross colour reduction (SXCR); data bit D5
Reduction off
Reduction on
SXCR = 0
SXCR = 1
Field selection (FSEL); data bit D6
50 Hz, 625 lines
60 Hz, 525 lines
FSEL = 0
FSEL = 1
Automatic field detection(AUFD); data bit D7
Field state directly controlled via FSEL
Automatic field detection
AUFD = 0
AUFD = 1
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