參數(shù)資料
型號: S29GL256N10FAI010
廠商: SPANSION LLC
元件分類: PROM
英文描述: MirrorBit Flash Family
中文描述: 16M X 16 FLASH 3V PROM, 100 ns, PBGA64
封裝: 13 X 11 MM, FBGA-64
文件頁數(shù): 85/95頁
文件大?。?/td> 3781K
代理商: S29GL256N10FAI010
86
S29GL-N
S29GL-N_00_B8 May 30, 2008
Da ta
Sh e e t
20. Advance Information on S29GL-R 65 nm MirrorBit Hardware
Reset (RESET#) and Power-up Sequence
Note
CE#, OE# and WE# must be at logic high during Reset Time.
Figure 20.1 Reset Timings
Note
The sum of tRP and tRH must be equal to or greater than tRPH.
Notes
1. VIO < VCC + 200 mV.
2. VIO and VCC ramp must be in sync during power-up. If RESET# is not stable for 300 s, the following conditions may occur: the device
does not permit any read and write operations, valid read operations return FFh, and a hardware reset is required.
3. Maximum VCC power up current is 20 mA (RESET# =VIL).
Figure 20.2 Power-On Reset Timings
Note
The sum of tRP and tRH must be equal to or greater than tRPH.
Table 20.1 Hardware Reset (RESET#)
Parameter
Description
Limit
Time
Unit
tRPH
RESET# Low to CE# Low
Min
35
s
tRP
RESET# Pulse Width
Min
200
ns
tRH
Time between RESET# (high) and CE# (low)
Min
200
ns
Table 20.2 Power-Up Sequence Timings
Parameter
Description
Limit
Time
Unit
tVCS
VCC Setup Time to first access
Min
300
s
tVIOS
VIO Setup Time to first access
Min
300
s
tRPH
RESET# Low to CE# Low
Min
35
s
tRP
RESET# Pulse Width
Min
200
ns
tRH
Time between RESET# (high) and CE# (low)
Min
200
ns
tRPH
CE#
RESET#
tRP
tRH
CE#
VCC
V IO
RESET#
t VIOS
t VCS
t RP
t RH
t RPH
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