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參數(shù)資料
| 型號： | S1C63466F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP8-144 |
| 文件頁數(shù)： | 19/135頁 |
| 文件大?。?/td> | 1053K |
| 代理商： | S1C63466F |
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S1C63466 TECHNICAL MANUAL
EPSON
107
CHAPTER 5: SUMMARY OF NOTES
Sound generator
(1) Since it generates a BZ signal that is out of synchronization with the BZE register, hazards may at
times be produced when the signal goes ON/OFF due to the setting of the BZE register.
(2) The one-shot output is only valid when the normal buzzer output is OFF (BZE = "0") and will be
invalid when the normal buzzer output is ON (BZE = "1").
(3) The buzzer signal is generated by dividing the OSC1 oscillation clock. Since the frequencies and times
that are described in this section are the values in the case of crystal oscillation (32.768 kHz, Typ.),
they differ when CR oscillation (60 kHz, Typ.) is selected.
SVD circuit
(1) To obtain a stable detection result, the SVD circuit must be ON for at least l00 sec. So, to obtain the
SVD detection result, follow the programming sequence below.
1. Set SVDON to "1"
2. Maintain for 100 sec minimum
3. Set SVDON to "0"
4. Read SVDDT
(2) The SVD circuit should normally be turned OFF because SVD operation increase current consump-
tion.
Interrupt
(1) The interrupt factor flags are set when the interrupt condition is established, even if the interrupt
mask registers are set to "0".
(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
(3) After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1
and SP2 are set with the software. Be sure to set the SP1 and SP2 in the initialize routine.
Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them is
set, all the interrupts including NMI are masked and interrupts cannot be accepted until the other one
is set.
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