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參數(shù)資料
| 型號： | S1C63466F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP8-144 |
| 文件頁數(shù)： | 122/135頁 |
| 文件大小： | 1053K |
| 代理商： | S1C63466F |
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S1C63466 TECHNICAL MANUAL
EPSON
79
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
A sample basic serial input/output portion connection is shown in Figure 4.11.3.1.
S1C63466
SCLK
SOUT
SIN
Input terminal
External
serial device
CLK
SOUT
SIN
READY
S1C63466
SCLK
SOUT
SIN
SRDY
External
serial device
CLK
SOUT
SIN
Input terminal
(a) Master mode
(b) Slave mode
Fig. 4.11.3.1 Sample basic connection of serial input/output section
4.11.4 Data input/output and interrupt function
The serial interface of S1C63466 can input/output data via the internal 8-bit shift register. The shift
register operates by synchronizing with either the synchronous clock output from the SCLK (P12)
terminal (master mode), or the synchronous clock input to the SCLK (P12) terminal (slave mode).
The serial interface generates an interrupt on completion of the 8-bit serial data input/output. Detection
of serial data input/output is done by counting of the synchronous clock SCLK; the clock completes
input/output operation when 8 counts (equivalent to 8 cycles) have been made and then generates an
interrupt.
The serial data input/output procedure is explained below:
(1) Serial data output procedure and interrupt
The S1C63466 serial interface is capable of outputting parallel data as serial data, in units of 8 bits.
By setting the parallel data to the data registers SD0–SD3 (FF72H) and SD4–SD7 (FF73H) and writing
"1" to SCTRG bit (FF70HD1), it synchronizes with the synchronous clock and the serial data is output
to the SOUT (P11) terminal. The synchronous clock used here is as follows: in the master mode,
internal clock which is output to the SCLK (P12) terminal while in the slave mode, external clock
which is input from the SCLK (P12) terminal.
Shift timing of serial data is as follows:
When negative polarity is selected for the synchronous clock (mask option):
The serial data output to the SOUT (P11) terminal changes at the falling edge of the clock input or
output from/to the SCLK (P12) terminal. The data in the shift register is shifted at the falling edge of
the SCLK signal when the SCPS register (FF71HD2) is "1" and is shifted at the rising edge of the
SCLK signal when the SCPS register is "0".
When positive polarity is selected for the synchronous clock (mask option):
The serial data output to the SOUT (P11) terminal changes at the rising edge of the clock input or
output from/to the SCLK (P12) terminal. The data in the shift register is shifted at the rising edge of
the SCLK signal when the SCPS register is "1" and is shifted at the falling edge of the SCLK signal
when the SCPS register is "0".
When the output of the 8-bit data from SD0 to SD7 is completed, the interrupt factor flag ISIF
(FFF3HD0) is set to "1" and an interrupt occurs. Moreover, the interrupt can be masked by the
interrupt mask register EISIF (FFE3HD0). However, regardless of the interrupt mask register setting,
the interrupt factor flag is set to "1" after output of the 8-bit data.
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